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[AK5602A] ms1285-e-00 2011/02 - 1 - features z suitable for three phase, 3 wired or 4 wired energy metering or energy monitoring application z provide less than 0.1 % active & reactive energy error over a dynamic range of 1000 to 1, compatible with iec 0.5s z provide instantaneous active power, reactive power and apparent power z provide voltage rms, current rms, voltage instantaneous value, current instantaneous value and power factor in each phase. z provide less than 0.5 % voltage rms, current rms and power factor error z provide very accurate 90 degree phase shifter over 45hz to 65hz input frequency range, which is used for reactive power calculation z provide minute input voltage monitoring function z wide phase adjust. range between v & i (11 ) z provide positive and negative power indication z built-in temperature sensor z single power supply (3 v or 5v) z 48lqfp operational summary AK5602A is one of the most advanced and functional lsis for multi phase energy measurement. current and voltage signals through ct, hall sensor, or shunt resistors are converted into digital signal with 18bit adc. instantaneous voltage and cu rrent in each phase is multiplied and is added in total phases. the value changes into active power after passing through lpf and added with the value of a light load register. after this value is compared with the value of rated standard value register, it outputs pulses in proportion to the calculation. regarding reactive power, input current is precisely shift by 90 degree and multipli ed with respective voltage input signal. it outputs pulses in the same manner of active power calculation. and apparent power can be selectively derived from either active power and reactive power calculation or vrms x irms calculation and it outputs pulses as the result of calculation. system block diagram vif v if vif AK5602A z active power ( pulse, register ) z reactive power ( pulse, register ) z apparent power ( pulse, register ) z voltage rms value, current rms value z instantaneous voltage value & current value z power factor z wide phase adjustment range between voltage and current ( 11 at 50hz) z temperature sensor ( c : celsius ) z single voltage power supply ( 3v or 5v) z 48p lqfp package lcd eeprom mpu comm. se ri a l if cif c_if ci f n 1 2 3 energy metering lsi for multi ph ase, high accurate application ak 5602a
[AK5602A] ms1285-e-00 2011/02 - 2 - ich 1 i1p i1n pga x1 to x32 sigma- delta mod. fir + rpl active power to frequency conversion + + rpst rpo tpst tpo i2p i2n vch 1 v1p fir v2p ich 2 vch 2 f1 f2 p xp -1 -xp xp+rpl - xp+tpl reference voltage vcom vrefo vrefi oscillator xout xin rst stby rdy serial to pararell conversion control sclk cs di do bvss avdd avss dvdd dvss reactive (apparent ) power to frequency conversion + + rqst rqo tqst tqo xq -1 -xq xq+rql -xq+tql ich 3 i3p i3n vch 3 v3p vin pga x1 to x4 f3 i2 v2 hpf p1 i1 v1 hpf 90 degree phase shifter q1 + q temp. sensor phase adj. dis tpl rql tql gain adj. lpf lpf rms value apparent power power factor s1 pf1 calculation block (ch1) p2 q2 s2 pf2 p3 q3 s3 pf3 i3 v3 calculation block (ch2) calculation block (ch3) test1 test2 test3 v3 frequency output v1 frequency output v2 frequency output vs sigma- delta mod. phase adj. gain adj. vn threshold x x x x x
[AK5602A] ms1285-e-00 2011/02 - 3 - 2. block feature block function pga (programmable gain amp) current input gain selection (from 1 to 32) voltage input gain selection (from 1 to 4) this pga becomes operative with rst =stby = ?h? sigma delta modulator sigma delta modulator with 3 channel differential inputs. this modulator becomes operative with rst =stby = ?h? phase adjuster this adjusts the phase diffe rence between current if and voltage if. this phase shifter becomes operative with rst =stby = ?h? fir filter lpf. this produces 18 bit adc da ta in current side an d 16 bit adc data in voltage side from th e sigma delta modulator. this filter becomes operative with rst =stby = ?h? hpf this hpf is a selectable filter. it removes the dc part arising from dc offset of adc or input signal. in a case of passing through the dc part of input signal, only dc offset o f adc can be removed by calibration command. this hpf is not selected in the default setting. this hpf becomes operative with rst =stby = ?h? gain adjustment values of in put current and input voltage can be adjusted against ideal values with a gain adjustment (full-scale) command. this adjustment becomes operative with rst =stby = ?h? 90 degree phase shifter 90-degree phase shifter. this shifter becomes operative with rst =stby = ?h? rms value calculator it calculates rm s value from an instantaneous signal. this calculator becomes operative with rst =stby = ?h? lpf lpf. this filter becomes operative with rst =stby = ?h? apparent power calculator apparent power can be derived from either vrms irms calculation or active power & reactive power calculation. this calculator becomes operative with rst =stby = ?h? power factor power factor can be derived from active power & apparent power calculation. power factor becomes operative with rst =stby = ?h? active energy to frequency conversion positive active energy or negative active energy is converted into respective frequency, which is proportional to its active energy. this block becomes operative with rst =stby =dis = ?h?
[AK5602A] ms1285-e-00 2011/02 - 4 - reactive energy to frequency conversion positive reactive energy or negative reactive energy is converted into respective frequency, which is prop ortional to its reactive energy. this block becomes operative with rst =stby =dis = ?h? block function temperature sensor this block measures the temperature of AK5602A. this block becomes operative with rst =stby =dis = ?h? frequency pulse outputs each voltage input is digitized acco rding to each threshold value, and digitized frequency is output. this block becomes operative with rst =stby = ?h? reference voltage generator this block generates 1.17v reference voltage. this block becomes operative with rst =stby = ?h? oscillator the crystal oscillator which os cillates around 12.9024mhz is connected. this block becomes operative with rst =stby = ?h? serial to parallel controller serial interface to cpu. this block becomes operative with rst = ?h? 2-1 block operation mode rst stby dis block operation mode l l l all blocks are off h l l only serial to parallel controller block is operative. h h l all blocks except power to frequency conversion blocks are operative. h h h all blocks are operative.
[AK5602A] ms1285-e-00 2011/02 - 5 - 3. pin description ai : analog input di : digital input pwr : power ao : analog output do : dig ital output gnd : ground pin number pin name type function 1 rst di reset input ( schmitt trigger input ) all circuits become inoperat ive with ?l? level input. a ll registers including input or output registers, controlling registers, data registers are initialized. 2 stby di standby input ( schmitt trigger input ) all circuits except serial pararell controller block become inoperative with ?l? level input after rst = ?h? it is possible to write in and read registers through the serial to the parallel conversion controller. 3 dis di disable input ( schmitt trigger input ) active energy to frequency co nversion and reactive energ y to frequency conversion blocks are stopped and data registers in those blocks are initialized with ?l? level input after rst =stby = ?h?. 4 tqo do negative reacti ve power pulse output ?h? pulse is output when accumulated negative reactive energy value is over the setting standard value. this pin becomes inoperative when rst = ?l? or stby = ?l? or dis = ?l?. 5 tqst do negative reactive energy flag output (this pin is not use d in iec mode.) ?h? level is output when an interval of output pulses at tqo is under the setting starting value. this pin becomes inoperative when rst = ?l? or stby = ?l? or dis = ?l?. 6 rqo do positive reactive energy pulse output ?h? pulse is output when accumulated positive reactive power value is over the setting standard value. this pin becomes inoperative when rst = ?l? or stby = ?l? or dis = ?l?. 7 rqst do positive reactive energy flag output (this pin is not used in iec mode.) ?h? level is output when an interval output pulses at rqo is under the setting starting value. this pin becomes inoperative when rst = ?l? or stby = ?l? or dis = ?l?.
[AK5602A] ms1285-e-00 2011/02 - 6 - pin number pin name type function 8 dvss gnd digital ground. 9 dvdd pwr digital power. 10 tpo do negative active energy pulse output. ?h? pulse is output when accumulated negative active power value is over the setting standard value. this pin becomes inoperative when rst = ?l? or stby = ?l? or dis = ?l?. 11 tpst do negative active power flag output. ?h? level is output when an interval of output pulses at tpo is under the setting starting value. this pin becomes inoperative when rst = ?l? or stby = ?l? or dis = ?l?. 12 test1 di internal use only. connects to dvss. 13 rpo do positive active energy pulse output ?h? pulse is output when accumulated positive active power value is over the setting standard value. this pin becomes inoperative when rst = ?l? or stby = ?l? or dis = ?l?. 14 rpst do positive active power flag output. ?h? level is output when an interval output pulses at rpo is under the setting starting value. this pin becomes inoperative when rst = ?l? or stby = ?l? or dis = ?l?. 15 test2 di internal use only. connects to dvss. 16 test3 di internal use only. connects to dvss. 17 bvss gnd silicon base re ference gnd. connects avss. 18 xout ao 19 xin ai crystal oscillator connection. connects 12.8 mhz oscillator. 20 avdd pwr analog power. 21 avss gnd analog ground. 22 vrefo ao reference voltage output, 1.17v it outputs with the reference to avss. this output usuall y connects to vrefi pin. connects 4.7uf (under 10uf) electrolytic capacitor and 0. 1uf ceramic capacitor between this pin and agnd. this output is an internal use only and should not be connected to circuits outside the ic.
[AK5602A] ms1285-e-00 2011/02 - 7 - pin number pin name type function 23 vrefi ai reference voltage input. it usually connects to vrefo. an outside vref is connected between this pin and avss in a case that an inside vref of the ic is not used. 24 vcom ao common voltage output, 1.17v. it feeds a common voltage to an internal block of the ic. it should not be connected to th e outside circuits of the lsi. connect 0.1uf ceramic capacitor between this pin and avss. 25 vs ao controlling voltage output for input switches. it generates the voltage wh ich controls input switches referenced to avss in on and off state. this is an internal use only. it should not be connected to the outside circuits of the ic. co nnects 0.1uf ceramic capacitor between this pin and avss. 26 vin ai voltage side common analog negative input. 27 v3p ai voltage side ch3 analog positive input. 28 v2p ai voltage side ch2 analog positive input. 29 v1p ai voltage side ch1 analog positive input. 30 nc nc no connection. connects to avss. 31 i1p ai current side ch1 analog positive input. 32 i1n ai current side ch1 analog negative input. 33 i2p ai current side ch2 analog positive input. 34 i2n ai current side ch2 analog negative input. 35 i3p ai current side ch3 analog positive input. 36 i3n ai current side ch2 analog negative input. 37 nc nc no connection. connects to avss. 38 rdy do reading approval pin of registers the content of registers can be read when this pin becomes ?low?. this pin becomes ?high? when rst = ?l? or stby = ?l? or dis = ?l?.
[AK5602A] ms1285-e-00 2011/02 - 8 - pin number pin name type function 39 cs di serial interface selection input (schmitt trigger input) serial interface become oper ative with ?l? level input at this pin while rst = ?h?. 40 sclk di serial data clock input 41 bvss gnd silicon base referenc e gnd. connects to avss. 42 dvss gnd digital ground. 43 dvdd pwr digital power. 44 di di serial data input this di pin becomes valid with cs = ?l? while rst = ?h? and it inputs data in synchronization with the risin g edge of the clock at sclk pin. stored data is transferre d into the respective register in the synchronization with the rising edge of cs . 45 do do serial data output this do pin becomes valid with cs = ?l? while rst = ?h? and it outputs data in synchronization with the falling edge of the clock at sclk pin. this do pin becomes a high impedance state except cs = ?l? while rst = ?h?. 46 f3 do v3 frequency output a rectangular wave produced by a waveform shapin g circuit is output. this pin becomes low level when rst = ?l? or stby = ?l?. 47 f2 do v2 frequency output a rectangular wave produced by a waveform shapin g circuit is output. this pin becomes low level when rst = ?l? or stby = ?l?. 48 f1 do v1 frequency output a rectangular wave produced by a waveform shapin g circuit is output. this pin becomes low level when rst = ?l? or stby = ?l?.
[AK5602A] ms1285-e-00 2011/02 - 9 - 4. electrical characteristics 4.1 absolute maximum rating item symbol min max unit reference dvdd -0.3 +6.5 power supply voltage avdd -0.3 +6.5 v ground level avss dvss bvss 0 v voltage reference level input current iin 10 ma except power pin analog input voltage1 v ina1 -0.3 (avdd)+0.3 v analog input voltage2 v ina2 -3.0 +3.0 v i1p, i1n, i2p, i2n, i3p, i3n, v1p, v2p, v3p, vin digital input voltage i ind -0.3 dvdd+0.3 v storage temperature t stg -50 125 c note ) it may cause a permanent damage to th e device if used beyond listed conditions.
[AK5602A] ms1285-e-00 2011/02 - 10 - 4.2 recommended operating conditions item symbol min typ max unit reference avdd 2.7 5.25 power supply voltage dvdd 2.7 5.25 v note 1 analog reference input voltage v ref 1.11 1.17 1.23 v note 2 analog input maximum voltage v ain max -1.0 1.0 v note 3 a nalog input volta g e v ain -fs +fs v note 4 operating tem p erature ta -40 85 c note 1: -0.1v dvdd - avdd +0.1v note 2: this is a case when outside reference voltage is connected to vrefi. 1.17v 5% note 3: this range of analog input signal is to be calculated. note 4: v ain = ( ainp ) - (ainn) ainp: v1p, v2p, v3p; ainn: vin gain 1 : -fs = -1.0v, +fs = 1.0v 2 : -fs = -0.5v, +fs = 0.5v 4 : -fs = -0.25v, +fs = 0.25v ainp: i1p, i2p, i3p; ainn: i1n, i2n, i3n gain 1 : -fs = -1.0v, +fs = 1.0v 2 : -fs = -0.5v, +fs = 0.5v - 8 : -fs = -0.125v, +fs = 0.125v - 16 : -fs = -0.0625v, +fs = 0.0625v - 24 : -fs = -0.0417v, +fs = 0.0417v - 32 : -fs = -0.03125v, +fs = 0.03125v z regarding the analog voltage input, adc outp uts a plus full scale code (7fffh ) against the input over a +fs input and outputs a minus full scale code (8000h) against the input under - fs. z regarding the analog current input, adc outp uts a plus full scale code (1ffffh) against the input over a +fs input and outputs a minus full scale code (20000h) against the input under - fs.
[AK5602A] ms1285-e-00 2011/02 - 11 - 4.3 analog characteristics conditions: ta=25 c, avdd=dvdd=5.0v, v ref = 1.17v, xclk = 12.9024mhz, signal frequency = 50hz, measur ed bandwidth = 10 to 1.5khz; unless otherwise specified. 4.3.1 pga voltage side item min typ max unit reference input range gain setting : 4 (12 db) 2 (6 db) 1 (0 db) 0.95 0.25 0.5 1.0 1.05 v p-p note 5 input impedance 350 k note 6 note 5: only applicable for v (voltage) input. th is is a full-scale value of analog input voltage (v ain = (ainp) - (ainn)). vin is usually conn ected to agnd and each analog input voltage is added with reference to vin. note 6: input impedance between ai np (v1p, v2p, v3p) and ainn (vin). minimum value is when gain is set at 4 (12db). input impedance is reversed proportional to the gain setting. current side item min typ max unit reference input range gain setting: 32 (30db) 24 (27.6db) 16 (24 db) 8 (18 db) 4 (12 db) 2 (6 db) 1 (0 db) 0.95 0.0313 0.0417 0.0625 0.125 0.25 0.5 1.0 1.05 v p-p note 7 input impedance 200 k note 8 note 7: only applicable for i(cu rrent) input (differential input) . this is a full-scale value of analog input voltage (v ain = (ainp) - (ainn)). note 8: input impedance between ainp (i 1p, i2p, i3p) and ainn (i1n, i2n, i3n). minimum value is when gain is set at 8 (18db). input impedance is reversed proportional to gain setting.
[AK5602A] ms1285-e-00 2011/02 - 12 - 4.3.2 adc voltage side item min typ max unit reference resolution 16 bit s/n+d 65 db note 9 isolation between current and voltage 100 db note 10 crosstalk between voltage channels 100 db power factor adjustment range between current and voltage -613.84 613.84 us note 11 power factor adjustment accuracy between current and voltage 1.24 us note 12 adc period 3.15 khz note 13 note 9: this is the value when analog input si gnal is applied at -6db of full scale value with pga = 0 db. this is the ratio between rms value of input signal and summation of rms values of all frequencies from 10hz to 1.5khz excluding the input signal. note 10: this is the isolation value between voltage side adc and current side adc. note 11: this is the delay adjustment range of voltage side against current side. + side setting delays starting poin t of a/d conversion at voltage side against starting point of a/d conversion at cu rrent side in the range of 0u s to +613.84us, while - side setting delays starting point of a/d conversion at current side against starting point of a/d conversion at voltage side in the range of 0us to +613.84us. this enables the delay adjustment range at voltage side against current side from -613.84us to +613.84us. please note that when the delay adjustment is changed from + to - or - to + during the operation of the ic, a/d conversion data becomes uncontinuous. note 12: delay adjustment step is 1.24us. note 13: adc period is 3.15khz at every channel.
[AK5602A] ms1285-e-00 2011/02 - 13 - current side item min typ max unit reference resolution 18 bit s/n+d 65 db note 14 isolation between current and voltage 100 db note 15 crosstalk between current channels 100 db adc period 3.15 khz note 16 note 14: this is the value when analog input signal is applied at -6db of full scale value with pga = 0 db. this is the ratio between rms value of input signal and summation of rms values of all frequencies from 10hz to 1.5khz excluding the input signal. note 15: this is the isolation value between voltage side adc and current side adc. note 16: adc period is 3.15khz at every channel. 4.3.3 reference voltage item min typ max unit reference vref output level 1.11 1.17 1.23 v note 17 v ref temperature drift 30 ppm/ c note 18 note 17: output level of vrefo. it outputs 1.17v 5% with reference to avss. note 18: the temperature drift of vrefo output level. 4.3.4 temperature sensor item min typ max unit reference temperature range -40 85 c resolution 1 c note 19 accuracy 5 c note 20 note 19: resolution value when the value of temperature register is read from the register. note 20: this is the difference between the value of temperature register and real value at 25 c.
[AK5602A] ms1285-e-00 2011/02 - 14 - 4.3.5 power supply item min typ1 typ2 max unit reference power consumption 18 40 70 mw note 21 standby current 1 1 20 ua note 21 note 21: typ1 is the value at avdd = dvdd = 3.0v and typ2 is the value at avdd = dvdd = 5.0v. consumption current is measured on condition of which all digital inputs are connected to dvdd or dvss and all an alog inputs are connected to analog input bias level. it does not contain ou tput current. avdd = dvdd = 2.7v to 5.25v. 4.3.6 filter characteristics ta = -40 to 85 c, avdd=dvdd=2.7v to 5.25v, xclk=12.9024 mhz (filter characteristics is proportional to the frequency of xclk.) 4.3.6.1 fir filter (lpf) item min typ max unit reference 0.008db 45 66 pass band +0.008db -0.910db 0 1500 hz attenuation level at stop band at 10.0khz 74.0 db 4.3.6.2 hpf item min typ max unit reference -3 db 1.3 -0.5 db 3.6 -0.1db 8.7 -0.004 db 45 frequency response -0.002 db 66 hz phase shift value 45 to 66hz 1.13 1.66 degree
[AK5602A] ms1285-e-00 2011/02 - 15 - 4.3.6.3 90 degree phase shifter item min typ max unit reference phase shift value 45 to 66hz 89.98 90 90.02 degree note 22 gain error 0 to 1500hz 0.001 db note 23 note 22: phase difference between two inputs. note 23: gain error between input and ou tput of 90 degree phase shifter. 4.3.6.4 iir filter ( lpf ) item min typ max unit reference pass band 0.1db 0 0.4 hz attenuation level at stop band at 100hz 60 db 4.3.7 dc characteristics ta = -40 to 85 c, avdd=dvdd=2.7 to 5.25v item symbol min typ max unit reference high level input voltage v ih 0.7(dvdd) v note 24 low level input voltage v il 0.3(dvdd) v note 24 high level output voltage iout=0.5ma for rpo/tpo/rqo/tqo iout=2ma v oh (dvdd)-0.4 low level output voltage iout=-0.5ma for rpo/tpo/rqo/tqo iout=-2ma v ol 0.4 v input leak current i in 10 ua note 24: except test1, test2, and test3 pins.
[AK5602A] ms1285-e-00 2011/02 - 16 - 4.3.8 switching characteristics ta=-40 to 85 c, avdd=dvdd=2.7~5.25v, cl=20pf, xclk=12.9024mhz item symbol pin min typ max unit reference serial clock frequency f sclk sclk 4 mhz t sckh sclk 100 ns fig.1 ?h? pulse width t outh rpo,tpo rqo,tqo 59.5 0.2 us fig.3 note 25 t sckl sclk 100 ns fig.1 t rstl rst 1 t stbl stby 1 ?l? pulse width t disl dis 1 us fig.4 t cckh cs sclk 100 hold time t ckdh sclk di 50 ns fig.1 t ckds sclk di 50 setup time t ccks cs sclk 100 ns fig.1 t ckdv scl k do 80 ns fig.2 data output t ckdz scl k do 200 note 25: in case of pulsw11-0=000h (default).
[AK5602A] ms1285-e-00 2011/02 - 17 - rpo tpo t outh fig.3 rst stby t rstl 0.7dvdd 0.3dvdd fig.4 t stbl 0.7dvdd 0.3dvdd t ccks 0.7dvdd 0.3dvdd t cc k h cs sc lk t sck h t sckl t ck ds t ckdh di 0.7dvdd 0.3dvdd fig.1 0.7dvdd 0.3dvdd t ccks 0.7dvdd 0.3dvdd t cc k h cs sc lk t sck h t sckl t ckdv t ck dz do fig.2 in writing in reading high-z high-z dis t disl rqo tqo (note) reading and writing control is executed by commands of control setting register, add.?21h?.
[AK5602A] ms1285-e-00 2011/02 - 18 - 5. function 5.1 power on sequence operation phase comment ph1 rst : l operation of all circuits includin g serial interface and oscillator circuits is halted and digital circuit s including input / output register, control register and data register ar e initialized. at the same time f1, f2, f3, rpo, tpo, rqo,tqo, tpst, rqst and tqst becomes ?l? level and do becomes high impedance state. ph2 stby : l rst : h a serial interface circuit (input / ou tput register) becomes active and it is possible to write in and read registers. ph3 dis : l stby : h rst : h all circuits except active power to frequency conversion circuit and reactive power to frequency conversi on circuit become active. at this moment, rpo, tpo, rqo, tqo, rpst, tpst, rqst and tqst keeps ?l? level. oscillator circuit starts oscillation with rst =stby = ?h? and adc sequence is started. it normally needs 300ms before oscillation frequency and hpf are stabilized . the accuracy of adc and calibration is not guaranteed during this period. ph4 dis : h stby : h rst : h all circuits become active, but the changing of the state from ph3 to ph4 must be done after 300ms are being elapsed in ph3 state. avdd=dvdd rst stby dis ph1 ph2 ph3 ph4 ph3 ph4 fig.5 power on sequence
[AK5602A] ms1285-e-00 2011/02 - 19 - 5.2 registers 5.2.1 writing data into registers it is possible to access a seri al interface circuit with rst = ?h?, cs = ?l?. by applying a serial clock at sclk pin, input data is written into an input shift register. input data consists of 7 bits of address, on e bit ?l? level writing co mmand and 16 bits data strings. the state of di is sampled at rising edge of sclk for 24 times after cs = ?l? and transferred into the shift register. 16 bits da ta, which have been written into input shift data register will be transferred to the corres ponding control register at the rising edge of cs . in a case that the number of clocks of sclk is either less than 24 times or more than 25 times, input data will not be transferred into the corresponding control register. the number of clocks of sclk should be applied for 24 times even if the writing data consist of less than 16 bits format. and sclk must be started at ?h? state and ended at ?h? state. cs sclk 1 2 8 9 23 24 710 di a6 a5 a0 l d15 d14 d1 d0 fig.6 wr iting timing to registers starting address (8bit) writing in data
[AK5602A] ms1285-e-00 2011/02 - 20 - 5.2.2 reading data from registers it is possible to access a serial interface circuit with rst = ?h?, cs = ?l?. by applying a serial clock at sclk pin, input data is written into an input shift register. input data consists of 7 bits of address, one-bit ?h? level readin g command is followed. the state of di is sampled at ri sing edge of sclk for 8 times after cs = ?l?, transferred into the shift register and specified the starting address. in the starting address, the first 7 bits show the address of the control register which data should be stored and the next 1 bit shows either reading or writing. if the bit is ?h?, it means reading. if the bit is ?l?, it means writing. in case that data specified with only one addre ss is read (when add. ?21h?, bit1=?1?), 16 bit data which is specified by reading indication re gister is loaded into the shift register from the controlling register at the first falling edge of sclk following after the starting address and data is output at do pin. after that, data is continuously output at every sclk?s falling edge and 16-bit data, which have been loaded into the output shift register are output. furthermore, the next 16-bit data at the ne xt address are output if sclk is input continuously. this makes it possible to read data from registers continuously without readdressing. if sclk is applied even after, data at the last address add. ?59h? being output, the lsi outputs ?l? as far as cs pin remains ?l?. do pin beco mes high impedance state when cs pin is controlled at ?h? state. in a case that cs pin becomes ?h? state before all data being output, do pin becomes high impedance state and reading procedure is halted. in addition, sclk must be started at ?h? state and ended at ?h? state. when the data loading period into the output register and data renewal period coincide each other, the bit15 (invalid) of data at add. ?21h? becomes ?h? level. the invalid bit at add. ?21h? keeps ?h? level until the content of add. ?21h? will have been read, and it will be cleared after the reading. cs sclk 1 2 8 9 23 24 710 di a6 a5 a0 h fig.7 reading timing from controlling registers startin g addr ess(8bit) readin g data output do d15 d14 d1 d0 hi-z hi-z "l" initialization of registers all registers are initialized and the initia l values are loaded with ?l? level at rst pin.
[AK5602A] ms1285-e-00 2011/02 - 21 - 5.2.3 mapping of controlling registers [readable and writable registers] initial value of controlling registers be low is set to comply with japanese standard. in a case that the lsi is used to comply with iec standard, initial value of some registers should be modified. please refer to the chap ter 5.5, which describes the way of the system calibration in iec mode. address a6-0 r/w symbol name initial value 00h 9999h 01h r/w rpr rp rated active power threshold value 00c9h 02h 9999h 03h r/w tpr tp rated active power threshold value 00c9h 04h 9999h 05h r/w rqr rq rated reactive power threshold value 00c9h 06h 9999h 07h r/w tqr tq rated reactive power threshold value 00c9h 08h r/w rpst/tpst/ rqst/tqst rp/tp/rq/tq starting power threshold value for japanese specification 1111h 09h r/w b2b b2 balance value 0000h 0ah r/w b3b b3 balance value 0000h 0bh r/w rpl/rql rp/rq light load value 0000h 0ch r/w tpl/tql tp/tq light load value 0000h 0dh r/w pfcn1 n1 power factor adjustment value 0000h 0eh r/w pfcn2 n2 power factor adjustment value 0000h 0fh r/w pfcn3 n3 power factor adjustment value 0000h 10h r/w pgav1/pgai1 pga1 gain 0401h 11h r/w pgav2/pgai2 pga2 gain 0401h 12h r/w pgav3/pgai3 pga3 gain 0401h 13h r/w vthr1/vthf1 f1 threshold value 2b2dh 14h r/w vthr2/vthf2 f2 threshold value 2b2dh 15h r/w vthr3/vthf3 f3 threshold value 2b2dh 16h r/w fulv1/fuli1 full scale adjustment 1 0000h 17h r/w fulv2/fuli2 full scale adjustment 2 0000h 18h r/w fulv3/fuli3 full scale adjustment 3 0000h 19h r/w 0000h 1ah r/w voff voltage offset 0000h 1bh r/w 0000h 1ch r/w ioff current offset 0000h 1dh r/w pwadd power addition able or disable control 0000h 1eh r/w sendou creeping current threshold value for iec specification 003ah 1fh r/w pulsw pulse width of output powers for iec specification 0000h 20h r/w func_set function setting 0000h 21h r/w contl_set control setting 0000h
[AK5602A] ms1285-e-00 2011/02 - 22 - [read only registers] address a6-0 r/w symbol name initial value 22h r v1ad v(voltage)1 instantaneous value 0000h 23h r v2ad v(voltage)2 instantaneous value 0000h 24h r v3ad v(voltage)3 instantaneous value 0000h 25h r i1had i(current)1 instantaneous value (upper bits) 0000h 26h r i2had i(current)2 instantaneous value (upper bits) 0000h 27h r i3had i(current)3 instantaneous value (upper bits) 0000h 28h r ilad i1/i2/i3 instantaneous value (lower bits) 0000h 29h r v1rms v(voltage)1 rms value 0000h 2ah r v2rms v(voltage)2 rms value 0000h 2bh r v3rms v(voltage)3 rms value 0000h 2ch r i1rms i(current)1 rms value 0000h 2dh r i2rms i(current)2 rms value 0000h 2eh r i3rms i(current)3 rms value 0000h 2f reserved 30h 0000h 31h r p1 p1 instantaneous active power 0000h 32h 0000h 33h r p2 p2 instantaneous active power 0000h 34h 0000h 35h r p3 p3 instantaneous active power 0000h 36h 0000h 37h r psum total instantaneous active power 0000h 38h 0000h 39h r q1 q1 instantaneous reactive power 0000h 3ah 0000h 3bh r q2 q2 instantaneous reactive power 0000h 3ch 0000h 3dh r q3 q3 instantaneous reactive power 0000h 3eh 0000h 3fh r qsum total instantaneous reactive power 0000h 40h 0000h 41h r ptotr all total instantaneous active power (receiving) 0000h 42h 0000h 43h r ptott all total instantaneous active power (transmitting) 0000h 44h 0000h 45h r qtotr all total instantaneous reactive power (receiving) 0000h 46h 0000h 47h r qtott all total instantaneous reactive power (transmitting) 0000h 48h r ppulse active energy pulse 0000h 49h r qpulse reactive energy pulse 0000h
[AK5602A] ms1285-e-00 2011/02 - 23 - address a6-0 r/w symbol name initial value 4ah r s1 s1 apparent power 0000h 4bh r s2 s2 apparent power 0000h 4ch r s3 s3 apparent power 0000h 4dh r 0000h 4eh r ssum total apparent power 0000h 4fh - - reserved 0000h 50h r rxpo rpo active po wer accumulated value 0000h 51h r txpo tpo active power accumulated value 0000h 52h r rxqo rqo reactive po wer accumulated value 0000h 53h r txqo tqo reactive po wer accumulated value 0000h 54h r pf1 1 power factor 0000h 55h r pf2 2 power factor 0000h 56h r pf3 3 power factor 0000h 57h r temp temperature 0080h 58h r/w temp_coef temp. adjustme nt coefficient (gain) 1c2ah 59h r/w toffset temp. adjustment coefficient (offset) 0000h
[AK5602A] ms1285-e-00 2011/02 - 24 - minute register mapping data bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 address a6-0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 initial value rpr15-8 00h (r/w) rpr7-0 9999h - - - - - - rpr25-24 01h (r/w) rpr23-16 00c9h tpr15-8 02h (r/w) tpr7-0 9999h - - - - - - tpr25-24 03h (r/w) tpr23-16 00c9h rqr15-8 04h (r/w) rqr7-0 9999h - - - - - - rqr25-24 05h (r/w) rqr23-16 00c9h tqr15-8 06h (r/w) tqr7-0 9999h - - - - - - tqr25-24 07h (r/w) tqr23-16 00c9h tqst3-0 rqst3-0 08h (r/w) tpst3-0 rpst3-0 1111h - - - - b2b11-8 09h (r/w) b2b7-0 0000h - - - - b3b11-8 0ah (r/w) b3b7-0 0000h rql7-0 0bh (r/w) rpl7-0 0000h tql7-0 0ch (r/w) tpl7-0 0000h - - - - - - pfcn1_9-8 0dh (r/w) pfcn1_7-0 0000h - - - - - - pfcn2_9-8 0eh (r/w) pfcn2_7-0 0000h - - - - - - pfcn3_9-8 0fh (r/w) pfcn3_7-0 0000h
[AK5602A] ms1285-e-00 2011/02 - 25 - data bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 address a6-0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 initial value - - pgai1_5-0 10h (r/w) - - - - - pgav1_2-0 0401h - - pgai2_5-0 11h (r/w) - - - - - pgav2_2-0 0401h - - pgai3_5-0 12h (r/w) - - - - - pgav3_2-0 0401h vthf1_7-0 13h (r/w) vthr1_7-0 2b2dh vthf2_7-0 14h (r/w) vthr2_7-0 2b2dh vthf3_7-0 15h (r/w) vthr3_7-0 2b2dh fuli1_7-0 16h (r/w) fulv1_7-0 0000h fuli2_7-0 17h (r/w) fulv2_7-0 0000h fuli3_7-0 18h (r/w) fulv3_7-0 0000h voff15-8 19h (r/w) voff7-0 0000h - - - - - - - - 1a (r/w) voff23-16 0000h ioff15-8 1bh (r/w) ioff7-0 0000h - - - - - - - - 1ch (r/w) ioff23-16 0000h - qssel s3dis s2dis s1dis q3dis q2dis q1dis 1dh (r/w) - - - - - p3dis p2dis p1dis 0000h - - - - - - - sendou8 1eh (r/w) sendou7-0 003ah rdiv1-0 qodis podis pulsw11-8 1fh (r/w) pulsw7-0 0000h
[AK5602A] ms1285-e-00 2011/02 - 26 - data bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 address a6-0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 initial value - - zsi3 zsi2 zsi1 zsv3 zsv2 zsv1 20h (r/w) cal pfsel ssel iec hpf temp fulli fullv 0000h invalid - - - - - - - 21h (r/w) - - rmsrd1-0 adrd1-0 rdy1-0 0000h v1ad15-8 22h (r) v1ad7-0 0000h v2ad15-8 23h (r) v2ad7-0 0000h v3ad15-8 24h (r) v3ad7-0 0000h i1ad17-10 25h (r) i1ad9-2 0000h i2ad17-10 26h (r) i2ad9-2 0000h i3ad17-10 27h (r) i3ad9-2 0000h - - - - - - - - 28h (r) - - i3ad1-0 i2ad1-0 i1ad1-0 0000h v1rms15-8 29h (r) v1rms7-2 - - 0000h v2rms15-8 2ah (r) v2rms7-2 - - 0000h v3rms15-8 2bh (r) v3rms7-2 - - 0000h i1rms15-8 2ch (r) i1rms7-0 0000h i2rms15-8 2dh (r) i2rms7-0 0000h i3rms15-8 2eh (r) i3rms7-0 0000h reserved 2fh (r) reserved 0000h
[AK5602A] ms1285-e-00 2011/02 - 27 - data bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 address a6-0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 initial value p1_15-8 30h (r) p1_7-0 0000h - - - - - - - - 31h (r) - - - - p1_19-16 0000h p2_15-8 32h (r) p2_7-0 0000h - - - - - - - - 33h (r) - - - - p2_19-16 0000h p3_15-8 34h (r) p3_7-0 0000h - - - - - - - - 35h (r) - - - - p3_19-16 0000h psum15-8 36h (r) psum7-0 0000h - - - - - - - - 37h (r) - - psum21-16 0000h q1_15-8 38h (r) q1_7-0 0000h - - - - - - - - 39h (r) - - - - q1_19-16 0000h q2_15-8 3ah (r) q2_7-0 0000h - - - - - - - - 3bh (r) - - - - q2_19-16 0000h q3_15-8 3ch (r) q3_7-0 0000h - - - - - - - - 3dh (r) - - - - q3_19-16 0000h qsum15-8 3eh (r) qsum7-0 0000h - - - - - - - - 3fh (r) - - qsum21-16 0000h
[AK5602A] ms1285-e-00 2011/02 - 28 - data bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 address a6-0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 initial value ptotr15-8 40h (r) ptotr7-0 0000h - - - - - - - - 41h (r) ptotr23-16 0000h ptott15-8 42h (r) ptott7-0 0000h - - - - - - - - 43h (r) ptott23-16 0000h qtotr15-8 44h (r) qtotr7-0 0000h - - - - - - - - 45h (r) qtotr23-16 0000h qtott15-8 46h (r) qtott7-0 0000h - - - - - - - - 47h (r) qtott23-16 0000h pd - ppulse13-8 48h (r) ppulse7-0 0000h qd - qpulse13-8 49h (r) qpulse7-0 0000h s1_15-8 4ah (r) s1_7-0 0000h s2_15-8 4bh (r) s2_7-0 0000h s3_15-8 4ch (r) s3_7-0 0000h ssum15-8 4dh (r) ssum7-0 0000h - - - - - - - - 4eh (r) - - - - - - ssum17-16 0000h reserved 4fh (r) reserved 0000h
[AK5602A] ms1285-e-00 2011/02 - 29 - data bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 address a6-0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 initial value rxpo15-8 50h (r) rxpo7-0 0000h txpo15-8 51h (r) txpo7-0 0000h rxqo15-8 52h (r) rxqo7-0 0000h txqo15-8 53h (r) txqo7-0 0000h - pf1_14-8 54h (r) pf1_7-0 0000h - pf2_14-8 55h (r) pf2_7-0 0000h - pf3_14-8 56h (r) pf3_7-0 0000h - - - - - - - - 57h (r) temp7-0 0080h - - - tcoef12-8 58h (r/w) tcoef7-0 1c2ah - - - - - - - - 59h (r/w) - - - toffset4-0 0000h
[AK5602A] ms1285-e-00 2011/02 - 30 - 5.2.4 controlling registers rated power threshold value setting (add. 00h, 01h, 02h, 03h, 04h, 05h, 06h, 07h) data bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 address a6-0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 initial value rpr15-8 (same as below) 00h (r/w) rpr7-0 (rated active power threshold value at receiving mode) 9999h - - - - - - rpr25-24 (same as below) 01h (r/w) rpr23-16 (rated active power threshold value at receiving mode) 00c9h tpr15-8 (same as below) 02h (r/w) tpr7-0 (rated active power threshold value at transmitting mode) 9999h - - - - - - tpr25-24 (same as below) 03h (r/w) tpr23-16 (rated active power threshold value at transmitting mode) 00c9h rqr15-8 (same as below) 04h (r/w) rqr7-0 (rated reactive power threshold value at receiving mode) 9999h - - - - - - rqr25-24 (same as below) 05h (r/w) rqr23-16 (rated reactive power threshold value at receiving mode) 00c9h tqr15-8 (same as below) 06h (r/w) tqr7-0 (rated reactive power threshold value at transmitting mode) 9999h - - - - - - tqr25-24 (same as below) 07h (r/w) tqr23-16 (rated reactive power threshold value at transmitting mode) 00c9h [rp rated active power threshold value] this is the threshold value for producing the pulse of active power at receiving mode. the value should be 0000000h w rpr 3ffffffh [tp rated active power threshold value] this is the threshold value for producing the pulse of active power at transmitting mode. 0000000h w tpr 3ffffffh [rq rated reactive power threshold value] th is is the threshold value for producing the pulse of reactive powe r at receiving mode. 0000000h w rqr 3ffffffh [tq rated reactive power thresh old value] this is the thre shold value for producing the pulse of reactive power at transmitting mode. 0000000h w tqr 3ffffffh the initial value of rp, tp, rq and tq is set to meet the japanese specification. 1000 pulses are output for one second when the half of full -scale signal is applied at each voltage and current input of three phases. it is needed to change these values into 3225h to meet iec specification. starting power threshold va lue setting ( add. 08h) this value should be modified to 0fffh to meet iec standard. data bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 a ddress a6 -0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 initial value tqst3-0 (tq starting power threshold value) rqst3-0 (rq starting power threshold value) 08h (r/w) tpst3-0 (tp starting power threshold value) rpst3-0 (rp starting power threshold value) 1111h
[AK5602A] ms1285-e-00 2011/02 - 31 - rp starting power threshold value setting setting value bit3 bit2 bit1 bit0 starting power threshold value (sec) function 0 0 0 0 0.70 0 0 0 1 0.75 0 0 1 0 0.80 0 0 1 1 0.85 0 1 0 0 0.90 0 1 0 1 0.95 0 1 1 0 1.00 0 1 1 1 1.05 when ?l? level pulse width at rpo pin is narrower than the starting power threshold value, the level at rpst pin becomes ?h? level at the next rising edge of rpo pulse. when ?l? level pulse width at rpo pin is wider than the starting power threshold value, the level at rpst pin becomes ?l? level after the starting power threshold value. 1 x x x 0 regardless of the value at bi t2 to bit0, ?0? second is selected as the starting power threshold value. the level of rpst becomes ?h? when the value of xp + rpl is positive. the level of rpst becomes ?l? when the value of xp + rpl is negative. tp starting power threshold value setting setting value bit7 bit6 bit5 bit4 starting power threshold value (sec) function 0 0 0 0 0.70 0 0 0 1 0.75 0 0 1 0 0.80 0 0 1 1 0.85 0 1 0 0 0.90 0 1 0 1 0.95 0 1 1 0 1.00 0 1 1 1 1.05 when ?l? level pulse width at tpo pin is narrower than the starting power threshold value, the level at tpst pin becomes ?h? level at the next rising edge of tpo pulse. when ?l? level pulse width at tpo pin is wider than the starting power threshold valu e, the level at tpst pin becomes ?l? level after the starting power threshold value. 1 x x x 0 regardless of the value at bit6 to bit4, ?0? second is selected as the starting power threshold value. the level of tpst becomes ?h? when the value of -xp + tpl is positive. the level of tpst becomes ?l? when the value of -xp + tpl is negative. rq starting power threshold value setting setting value bit11 bit10 bit9 bit8 starting power threshold value (sec) function 0 0 0 0 0.70 0 0 0 1 0.75 0 0 1 0 0.80 0 0 1 1 0.85 0 1 0 0 0.90 0 1 0 1 0.95 0 1 1 0 1.00 0 1 1 1 1.05 when ?l? level pulse width at rqo pin is narrower than the starting power threshold value, the level at rqst pin becomes ?h? level at the next rising edge o f rqo pulse. when ?l? level pulse width at rqo pin is wider than the starting power threshold value, the level at rqst pin becomes ?l? level af ter the starting power threshold value. 1 x x x 0 regardless of the value at bit10 to bit8, ?0? second is selected as the starting power threshold value. the level of rqst becomes ?h? when the value of xq + rql is positive. the level of rqst becomes ?l? when the value of xq + rql is negative.
[AK5602A] ms1285-e-00 2011/02 - 32 - tq starting power threshold value setting setting value bit15 bit14 bit13 bit12 starting power threshold value (sec) function 0 0 0 0 0.70 0 0 0 1 0.75 0 0 1 0 0.80 0 0 1 1 0.85 0 1 0 0 0.90 0 1 0 1 0.95 0 1 1 0 1.00 0 1 1 1 1.05 when ?l? level pulse width at tqo pin is narrower than the starting power thre shold value, the level at tqst pin becomes ?h? level at the next rising edge of tqo pulse. when ?l? level pulse width at tqo pin is wider than the starting power threshold value, the level at tqst pin becomes ?l? level after the starting power threshold value. 1 x x x 0 regardless of the value at bit14 to bit12, ?0? second is selected as the starting po wer threshold value. the level of tqst becomes ?h? when the value of -xq + tql is positive. the level of tqst becomes ?l? when the value of -xq + tql is negative. initial value of starting power threshold value of tp, rp, tq and rq is set at 0.75 second. rpo(tpo,rqo,tqo) rpst (tpst,rqst,tqst) when starting power threshold value is set to ?0 ? second, 0. 75 s fig.6 output waveform of rpst(tpst,rqst,tqst) rpo (tpo,rqo,tqo) when starting power threshold value is s et ?0. 75? second in this case, rpst,tps t,rqst,tqst the polarity of xp+r pl (-xp+tpl,xq+rql,-xq+tql) 1.0 s 0.5 s 1.0 s 1.0 s 0. 5 s 0.5 s 0.5s rpo(tpo,rqo ,tqo) output
[AK5602A] ms1285-e-00 2011/02 - 33 - balance value setting (add. 09h, 0ah) data address a6-0 bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 initial value 09h (r/w) - - - - b2 balance value x000h 0ah (r/w) - - - - b3 balance value x000h b2 balance value: the value to adjust the gain of v2 against v1 b3 balance value: the value to adjust the gain of v3 against v1 the gain can be adjusted from 0 times to (2-1/2048) times. when the value is ?000h ?, the gain is ?1?. the value should be 000h b2 balance value, b3 balance value fffh setting value gain 7ffh 1+ 1/2 + 1/4 + 1/8 + + 1/2048 400h 1+ 1/2 (1.5) 200h 1+ 1/4 (1.25) 1ffh 1+ 1/8 + 1/16 + + 1/2048 100h 1+ 1/8 (1.125) 0ffh 1+ 1/16 + 1/32 + + 1/2048 001h 1+ 1/2048 000h 1 fffh 1- 1/2048 ffeh 1 ? 1/1024 f01h 1 - 1/16 - 1/32 - - 1/2048 f00h 1 - 1/8 (0.875) e00h 1 - 1/4 (0.75) c00h 1 - 1/2 (0.5) 800h 1 - 1 (0) do not set the value to 800h. this value makes the scale ?0?, which is invalid. initial value of b2 balance and b3 balance is set at 1.
[AK5602A] ms1285-e-00 2011/02 - 34 - light load value setting (add. 0bh, 0ch) data address a6-0 bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 initial value 0bh(r/w) rq light load value rp light load value 0000h 0ch(r/w) tq light load value tp light load value 0000h rp light load value, rq light load value: the valu e is used to adjust the offset at rp side or rq side in light load mode. value offset 7fh +31.75 7eh +31.5 : 01h +0.25 00h 0 ffh -0.25 : 81h -31.75 80h -32 tp light load value, tq light load value: the valu e is used to adjust the offset at tp side or tq side in light load mode. value offset 7fh +31.75 7eh +31.5 : 01h +0.25 00h 0 ffh -0.25 : 81h -31.75 80h -32 the initial value of each light load is set at ?0?.
[AK5602A] ms1285-e-00 2011/02 - 35 - power factor adjustment value setting (add. 0dh, 0eh, 0fh) data bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 address a6-0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 initial value - - - - - - pfcn1_9-8 (n1_adj.) 0dh (r/w) pfcn1_7-0 (n1_adj.) 0000h - - - - - - pfcn2_9-8 (n2_adj) 0eh (r/w) pfcn2_7-0 (n2_adj) 0000h - - - - - - pfcn3_9-8 (n3_adj) 0fh (r/w) pfcn3_7-0 (n3_adj) 0000h n1_adjust: this value is used to delay the star ting point of ad conversion at voltage side against current side in the ad conversion of [ (i1p) ? (i1n), (v1p) ? (vin) ]. value delay (xclk=12.9024mhz) 1efh 7920 xclk (613.84us) 1eeh 7904 xclk (612.60us) 01h 16 xclk (1.24us) 00h 0 xclk (0us) 3ffh -16 xclk (-1.24us) 212h -7904 xclk (-612.60us) 211h -7920 xclk (-613.84us) n2_adjust: this value is used to delay the star ting point of ad conversion at voltage side against current side in the ad conversion of [ (i2p) ? (i2n), (v2p) ? (vin) ]. value delay (xclk=12.9024mhz) 1efh 7920 xclk (613.84us) 1eeh 7904 xclk (612.60us) 01h 16 xclk (1.24us) 00h 0 xclk (0us) 3ffh -16 xclk (-1.24us) 212h -7904 xclk (-612.60us) 211h -7920 xclk (-613.84us) n3_adjust: this value is used to delay the star ting point of ad conversion at voltage side against current side in the ad conversion of [ (i3p) ? (i3n), (v3p) ? (vin) ]. value delay (xclk=12.9024mhz) 1efh 7920 xclk (613.84us) 1eeh 7904 xclk (612.60us) 01h 16 xclk (1.24us) 00h 0 xclk (0us) 3ffh -16 xclk (-1.24us) 212h -7904 xclk (-612.60us) 211h -7920 xclk (-613.84us) in a case that the value which is more than ?1ef h? is set at the above register, the delay will be 7920xclk . and if the value is less than ?211h?, the delay will be -7920xclk. initial value of each power factor adjustment value is set ?0?, which means no adjustment.
[AK5602A] ms1285-e-00 2011/02 - 36 - pga setting(add. 10h, 11h, 12h) data bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 address a6-0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 initial value - - pgai1_5-0 (ch1 current side pga) 10h (r/w) - - - - - pgav1_2-0 (ch1 voltage side pga) 0401h - - pgai2_5-0 (ch2 current side pga) 11h (r/w) - - - - - pgav2_2-0 (ch2 voltage side pga) 0401h - - pgai3_5-0 (ch3 current side pga) 12h (r/w) - - - - - pgav3_2-0 (ch3 voltage side pga) 0401h pgav1 (bit2 ? 0): to select ch1voltage side pga value bit2 bit1 bit0 gain analog input full scale voltage 0 0 0 x1 1.0v 0 0 1 x1 1.0v 0 1 0 x2 0.5v 0 1 1 x3 0.333v 1 0 0 x4 0.25v pgai1 (bit13 ? 8): to select ch1 current side pga value bit13 bit12 bit11 bit10 bit9 bit8 gain analog input full scale voltage 0 0 0 0 0 0 x1 1.0v 0 0 0 0 0 1 x1 1.0v 0 0 0 0 1 0 x2 0.5v 0 0 0 0 1 1 x3 0.333v 0 0 0 1 0 0 x4 0.25v 0 0 0 1 0 1 x5 0.20v - - - - - - - - 0 0 1 0 0 0 x8 0.125v - - - - - - - - 0 0 1 1 0 0 x12 0.0833v - - - - - - - - 0 1 0 0 1 0 x18 0.0556v - - - - - - - - 0 1 1 0 0 0 x24 0.0417v - - - - - - - - 0 1 1 1 1 1 x31 0.0323v 1 0 0 0 0 0 x32 0.03125v
[AK5602A] ms1285-e-00 2011/02 - 37 - pgav2 (bit2-0): to select ch2 voltage side pga value bit2 bit1 bit0 gain analog input full scale voltage 0 0 0 x1 1.0v 0 0 1 x1 1.0v 0 1 0 x2 0.5v 0 1 1 x3 0.333v 1 0 0 x4 0.25v pgai2 (bit13-8): to select ch2 current side pga value bit13 bit12 bit11 bit10 bit9 bit8 gain analog input full scale input 0 0 0 0 0 0 x1 1.0v 0 0 0 0 0 1 x1 1.0v 0 0 0 0 1 0 x2 0.5v 0 0 0 0 1 1 x3 0.333v 0 0 0 1 0 0 x4 0.25v 0 0 0 1 0 1 x5 0.20v - - - - - - - : 0 0 1 0 0 0 x8 0.125v - - - - - - - : 0 0 1 1 0 0 x12 0.0833v - - - - - - - : 0 1 0 0 1 0 x18 0.0556v - - - - - - - : 0 1 1 0 0 0 x24 0.0417v - - - - - - - : 0 1 1 1 1 1 x31 0.0323v 1 0 0 0 0 0 x32 0.03125v pgav3 (bit2-0): to select ch3 voltage side pga value bit2 bit1 bit0 gain analog input full scale input 0 0 0 x1 1.0v 0 0 1 x1 1.0v 0 1 0 x2 0.5v 0 1 1 x3 0.333v 1 0 0 x4 0.25v
[AK5602A] ms1285-e-00 2011/02 - 38 - pgai3 (bit13-8): to select ch3 current side pga value bit13 bit12 bit11 bit10 bit9 bit8 gain analog input full scale voltage 0 0 0 0 0 0 x1 1.0v 0 0 0 0 0 1 x1 1.0v 0 0 0 0 1 0 x2 0.5v 0 0 0 0 1 1 x3 0.333v 0 0 0 1 0 0 x4 0.25v 0 0 0 1 0 1 x5 0.20v - - - - - - - - 0 0 1 0 0 0 x8 0.125v - - - - - - - - 0 0 1 1 0 0 x12 0.0833v - - - - - - - - 0 1 0 0 1 0 x18 0.0556v - - - - - - - - 0 1 1 0 0 0 x24 0.0417v - - - - - - - - 0 1 1 1 1 1 x31 0.0323v 1 0 0 0 0 0 x32 0.03125v initial value of voltage side pga on each phase is set x1 and initial value of current side pga on each phase is set x4. threshold value of frequency pulse output setting (add. 13h, 14h, 15h) data bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 address a6-0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 initial value vthf1_7-0 (f1 falling threshold) 13h (r/w) vthr1_7-0 (f1 rising threshold) 2b2dh vthf2_7-0 (f2 falling threshold) 14h (r/w) vthr2_7-0 (f2 rising threshold) 2b2dh vthf3_7-0 (f3 falling threshold) 15h (r/w) vthr3_7-0 (f3 rising threshold) 2b2dh f1 rising threshold value: this is the rising threshold value of f1 output to determine the frequency based on ad conversion value of v1(voltage input1). f1pin outputs ?h? level over the threshold value. the value should be 00h vth1r 7fh. initial value is set about 70% of voltage input1 at initial value of rated active power register. value threshold 7fh 7f00h 7eh 7e00h - - 02h 0200h 01h 0100h 00h 0000h
[AK5602A] ms1285-e-00 2011/02 - 39 - f1 falling threshold value: this is the falling threshold value of f1 output to determine the frequency based on ad conversion value of v1 (voltage input1). f1pin outputs ?l? level under the threshold value. the value should be 00h vth1f 7fh. initial value is set about 68% of voltage input at initial value of rated active power register in japanese specification. value threshold 7fh 7f00h 7eh 7e00h - - 02h 0200h 01h 0100h 00h 0000h the rising threshold value and falling threshold value of f2 and f3 are set in the same manner of f1 and have the same initial values of f1. in addition, it is ignored that even if ?1? is written into the ?bit7? of the threshold register. full scale adjustment value setting (add. 16h, 17h, 18h) data bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 address a6-0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 initial value fuli1_7-0 (current side ch1 full scale adjustment) 16h (r/w) fulv1_7-0 (voltage side ch1 full scale adjustment) 0000h fuli2_7-0 (current side ch2 full scale adjustment) 17h (r/w) fulv2_7-0 (voltage side ch2 full scale adjustment) 0000h fuli3_7-0 (current side ch3 full scale adjustment) 18h (r/w) fulv3_7-0 (voltage side ch3 full scale adjustment) 0000h this register is to adjust the variations prod uced by pga and / or vref from ideal value so that the result of adc has an ideal adc code when a half of full-scale dc voltage, 0.5 v is applied to each voltage and current channel. when using this function, the gain of all voltage channels should be the same va lue as well as the gain of all current channels. the gain between current and voltage can be changed. it sh ould be very careful for using this function because after the adjustment, every calculation including an instantaneous value, rms value and active & reactive power is affected. the adjustment of gain on voltage side is performed by setting ?1? to bit0, fullv of function setting register,add.?20h?. and the adjustment of gain on current side is performed by setting ?1? to ?bit1?, fulli of function setting register,add.?20h?. after the execution of this command, the adjustment value can be read from add. ?16h?, ?17h?, ?18h? respectively. it is also possible to set the values as well by writing the values into these registers directly. refer to the table below to co nfirm the relationship between setting value and adjustment value.
[AK5602A] ms1285-e-00 2011/02 - 40 - value gain 7fh (1024+127)/1024 = 1.124023 7eh (1024+126)/1024 = 1.123047 01h (1024+1)/1024 = 1.0009766 00h (256+0)/ 256= 1.00 ffh (1024-1)/1024 = 0.999023 feh (1024-2)/1024 = 0.998047 81h (1024-127)/1024 = 0.875976 80h (1024-128)/1024 = 0.875 v(voltage) offset adjustment setting (add. 19h, 1ah) data bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 address a6-0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 initial value voff15-8 (v offset middle) 19h (r/w) voff7-0 (v offset lower) 0000h - - - - - - - - 1a (r/w) voff23-16 (v offset higher) 0000h this register is for setting offset value of adc at voltage side. the calibration is executed by setting ?1? to bit7, cal bit of function setting register,add.?20h?. it is possible to read the v offset value after the calibration. i(current) offset adjustment setting (add. 1bh, 1ch) data bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 address a6-0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 initial value ioff15-8 (i offset middle) 1bh (r/w) ioff7-0 (i offset lower) 0000h - - - - - - - - 1ch (r/w) ioff23-16 (i offset higher) 0000h this register is for setting offset value of adc at current side. the calibration is executed by setting ?1? to bit7, cal bit of function setting re gister, add. ?20h?. it is possible to read the i offset value after the calibration.
[AK5602A] ms1285-e-00 2011/02 - 41 - power addition ?disable? setting (add. 1dh) data bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 address a6-0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 initial value - qssel s3dis s2dis s1dis q3dis q2dis q1dis 1dh (r/w) - - - - - p3dis p2dis p1dis 0000h this register enables the addition control of active power (p1/p2/p3), reactive power (q1/q2/q3) and apparent power (s1/s2/s3) when power summation is executed. when ?1? is set to the corresponding bit, the addition of the corresponding channel is canceled. initial setting is that power at each channel is summed in active powe r, reactive power and apparent power. and qssel, bit14 is to select either reactive power pulse, ?0? or apparent power pulse,?1?. the initial setting of qssel is reactive power pulse. iec creeping value setting (add. 1eh) data bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 address a6-0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 initial value - - - - - - - sendou8 1eh (r/w) sendou7-0 003ah this register enables to set ?0? at power input to pulse conversion block when the value of xp =p1+p2+p3, xq=q1+q2+q3 or xs=s1+s2+s3 is less than the setting value. initial value is ?3ah?. this means that power inpu t to pulse conversion block is set ?0? when the summation of power each channel is le ss than 0.0075% of full-scale value. since this value is writable, it is possible to modify the value. iec power pulse width setting (add. 1fh) data bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 address a6-0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 initial value rdiv1-0 qodis podis pulsw11-8 (iec power pulse width higher) 1fh (r/w) pulsw7-0 (iec power pulse width lower) 0000h pulsw11-0 (bit11-0): this determines the iec compliant power pulse width. the pulse width will be 59.5us x (setting value +1). it is possi ble to set the pulse width between 59.5us and 243.7ms. the initial value of pulse width is 59.5us, which comply with the japanese standard. podis (bit12): active power pulse output disable. this stops the output of active power pulse when ?1? is set. this does not stop the procedure of the conversion from power to pulse. qodis (bit13): reactive power / a pparent power pulse output disable. this stops the output of reactive power / apparent power when ?1? is set. this does not stop the procedure of the conversion from power to pulse. initial value of podis and qodis is set to ?0? respectively. rdiv1-0 (bit15, bit14): this determines the fr equency of accumulated addition. the frequency becomes 16.8khz if the value is set ?00?,(initial value), becomes 8.4khz if the value is set ?01? and becomes 4.2khz if th e value is set ?10?.
[AK5602A] ms1285-e-00 2011/02 - 42 - function setting (add. 20h) data bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 address a6-0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 initial value - - zsi3 zsi2 zsi1 zsv3 zsv2 zsv1 20h (r/w) cal pfsel ssel iec hpf temp fulli fullv 0000h fullv (bit0): to set ?1? in this bit when the full-scal e adjustment for voltage side is to be executed. when the adjustment is completed su ccessfully, this bit becomes ?0? automatically. the initial value of this bit is set ?0?. fulli (bit1): to set ?1? in this bit when the full-scal e adjustment for current side is to be executed. when the adjustment is completed, this bit becomes ?0? automatically. the initial value of this bit is set ?0?. temp (bit2): to set ?1? in this bit when the measuremen t of the temperature of the lsi is to be executed. when the measurement is completed, this bit becomes ?0? automatically. the initial value of this bit is set ?0?. hpf (bit3) : to set ?1? in this bit when hpf is inse rted into each voltage input and current input. this setting is enabled for all channels si multaneously. the initial value of this bit is set ?0?. iec (bit4) : to set ?1? in this bit when iec value ,a dd.?1eh? is used as the creeping judgment value. the initial value of this bit is set ?0 ?, which means that the creeping judgment value complies with the japanese standard. ssel (bit5) : this bit is to select which type of apparent power is used. one is that the apparent power is derived from the calculation of active power and reactive power. the other is derived from the calculation of rms voltage value and rms current value. the initial value is set ?0?, which means that the apparent power is derived from the calc ulation of active power and reactive power. pfsel (bit6) : in the calculation of power factor, this bit is to select which type of apparent power is used. the first one is to use the appare nt power, which is derived from the calculation of active power and reacti ve power. the other is to select th e apparent power, which is derived from rms voltage and rms current. the initial valu e is set ?0?, which means that the apparent power is derived from the calculation of active power and reactive power. cal (bit7) : to set ?1? in this bit when the calibrati on of the adc at voltage side and current side is to be executed. when the calibration is completed successfully , this bit becomes ?0? automatically. the initial value of this bit is set ?0?. zsv1-zsv3 (bit8-bit10) : when setting each voltage input from ch1 through ch3 in a short mode, the corresponding bit should be set ?1?. initial value is set ?0?, which means that the corresponding bit is set not in a short mode. zsi1-zsi3 (bit11-bit13 ): when setting each current input from ch1 through ch3 in a short mode, the corresponding bit should be set ?1?. initial value is set ?0?, which means that the corresponding bit is set not in a short mode.
[AK5602A] ms1285-e-00 2011/02 - 43 - control setting (add. 21h) data bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 address a6-0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 initial value invalid - - - - - - - 21h (r/w) - - rmsrd1-0 adrd1-0 rdy1 rdy0 0000h rdy1-0 (bit1, bit0) : these bits assign rdy pin of the lsi to the one of the instantaneous value registers, rms value registers or other read-onl y registers. ?00? (initial value) is for rms registers,?01? is for instantaneous register s, ?10? or ?11? is for other read-only registers ,add.?22h? to ?57h?. there is no need rdy_control for readable and writable registers, add. ?00h? to ?21h?, ?58h? and ? 59h?. when the collision is occu rred between reading and writing without rdy control, invalid (bit15) bit is set. this means that wrong data had been read. initial value of invalid bit is ?00?, which is rdy control for rms. adrd1-0 (bit3, bit2) assign the renewal frequency of instantaneous values. ?00? means that the renewal frequency is 3.15khz, ?01? is 1.575khz frequency, ?10? is 0.7875khz. initial value is 3.15khz. rmsrd1-0 (bit5, bit4) assign the renewal frequency of rms values. ?00? means that the renewal frequency is 3.15khz, ? 01? is 1.575khz frequency, ?10? is 0.7875khz. initial value is 3.15khz. invalid (bit15) is set when the collision is occurred between reading and writing controlling registers. when invalid bit is set, it is needed to read the corresponding data again. this invalid bit is cleared when this bit is read. instantaneous value (add. 22h, 23h, 24h, 25h, 26h, 27h, 28h) data bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 address a6-0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 initial value v1ad15-8 (higher bits of ch1 instantaneous voltage) 22h (r) v1ad7-0 (lower bits of ch1 instantaneous voltage) 0000h v2ad15-8(higher bits of ch2 instantaneous voltage) 23h ( r ) v2ad7-0 (lower bits of ch2 instantaneous voltage) 0000h v3ad15-8(higher bits of ch3 instantaneous voltage) 24h ( r ) v3ad7-0 (lower bits of ch3 instantaneous voltage) 0000h i1ad17-10(higher bits of ch1 instantaneous current) 25h ( r ) i1ad9-2 (lower bits of ch 1 instantaneous current) 0000h i2ad17-10(higher bits of ch2 instantaneous current) 26h (r) i2ad9-2 (lower bits of ch 2 instantaneous current) 0000h i3ad17-10(higher bits of ch3 instantaneous current) 27h ( r ) i3ad9-2 (lower bits of ch 3 instantaneous current) 0000h - - - - - - - - 28h (r ) - - i3ad1-0(lowest bits o f ch3 instant. current) i2ad1-0(lowest bits of ch2 instant. current) i1ad1-0(lowest bits o f ch1 instant. current) 0000h these registers store the instantaneous value of each input voltage and current. voltage is expressed in 16bit format and current is expressed in 18bit format.
[AK5602A] ms1285-e-00 2011/02 - 44 - rms value (add. 29h, 2ah, 2bh, 2ch, 2dh, 2eh) data bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 address a6-0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 initial value v1rms15-8 (higher bits of ch1 voltage rms value) 29h ( r ) v1rms7-2 (lower bits of ch1 voltage rms value) - - 0000h v2rms15-8 (higher bits of ch2 voltage rms value) 2ah ( r ) v2rms7-2 (lower bits of ch2 voltage rms value) - - 0000h v3rms15-8 (higher bits of ch3 voltage rms value) 2bh ( r ) v3rms7-2 (lower bits of voltage rms value) - - 0000h i1rms17-10 (higher bits of ch1 current rms value) 2ch ( r ) i1rms9-2(lower bits of ch1 current rms value) 0000h i2rms17-10(higher bits of ch2 current rms value) 2dh ( r ) i2rms9-2(lower bits of ch2 current rms value) 0000h i3rms17-10(higher bits of ch3 current rms value) 2eh ( r ) i3rms9-2(lower bits of ch3 current rms value) 0000h these registers store the rms value of each input voltage and each input current. voltage is expressed in 14 bit format and current is expressed in 16 bit format. active power value (add. 30h, 31h, 32h, 33h, 34h, 35h, 36h, 37h) data bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 address a6-0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 initial value p1_15-8 (higher bits of ch1 active power) 30h ( r ) p1_7-0 (lower bits of ch1 active power) 0000h - - - - - - - - 31h ( r ) - - - - p1_19-16 (highest bits of ch1 active power) 0000h p2_15-8 (higher bits of ch2 active power) 32h ( r ) p2_7-0 (lower bits of ch2 active power) 0000h - - - - - - - - 33h ( r ) - - - - p2_19-16 (highest bits of ch2 active power) 0000h p3_15-8 (higher bits of ch3 active power) 34h ( r ) p3_7-0 (lower bits of ch3 active power) 0000h - - - - - - - - 35h ( r ) - - - - p3_19-16(highest bits of ch3 active power) 0000h psum15-8(higher bits of total active power (p1+p2+p3 )) 36h ( r ) psum7-0(lower bits of total active power (p1+p2+p3)) 0000h - - - - - - - - 37h ( r ) - - psum21-16(hi ghest bits of total active power(p1+p2+p3)) 0000h these registers store the active power value of ea ch input channel. each active power value is expressed in 20 bit format and total active power value is ex pressed in 22 bit format.
[AK5602A] ms1285-e-00 2011/02 - 45 - reactive power value (add. 38h, 39h, 3ah, 3bh, 3ch, 3dh, 3eh, 3fh) data bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 address a6-0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 initial value q1_15-8 (higher bits of ch1 reactive power) 38h ( r ) q1_7-0 (lower bits of ch1 reactive power) 0000h - - - - - - - - 39h ( r ) - - - - q1_19-16 (highest bits of ch1 reactive power) 0000h q2_15-8 (higher bits of ch2 reactive power) 3ah ( r ) q2_7-0 (lower bits of ch2 reactive power) 0000h - - - - - - - - 3bh ( r ) - - - - q2_19-16 (highest bits of ch2 reactive power) 0000h q3_15-8 (higher bits of ch3 reactive power) 3ch ( r ) q3_7-0 (lower bits of ch3 reactive power) 0000h - - - - - - - - 3dh ( r ) - - - - q3_19-16 (highest bits of ch3 reactive power) 0000h qsum15-8 (higher bits of total reactive power (q1+q2+q3)) 3eh ( r ) qsum7-0 (lower bits of total reactive power (q1+q2+q3)) 0000h - - - - - - - - 3fh ( r ) - - qsum21-16(highest bits of to tal reactive power (q1+q2+q3)) 0000h these registers store the reactive power value of each input channel. each reactive power value is expressed in 20 bit format and total reactive power value is expressed in 22 bit format. all total active power valu e(add. 40h, 41h, 42h, 43h) data bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 address a6-0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 initial value ptotr15-8 (higher bits of all total receiving active power) 40h (r) ptotr7-0 (lower bits of all to tal receiving active power) 0000h - - - - - - - - 41h (r) ptotr23-16 (highest bits of all total receiving active power) 0000h ptott15-8 (higher bits of all total transmitting active power) 42h (r) ptott7-0 (lower bits of all total transmitting active power) 0000h - - - - - - - - 43h (r) ptott23-16 (highest bits of all total transmitting active power) 0000h these registers store all total receiving acti ve power value (p1+p2+p3+rpl) and all total transmitting active power value (p1+p2+p3+tpl) . the value is expressed in 24 bit format
[AK5602A] ms1285-e-00 2011/02 - 46 - all total reactive power valu e (add. 44h, 45h, 46h, 47h) data bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 address a6-0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 initial value qtotr15-8 (higher bits of all total receiving reactive power) 44h (r ) qtotr7-0 (lower bits of all total receiving reactive power) 0000h - - - - - - - - 45h (r ) qtotr23-16 (highest bits of all total receiving reactive power) 0000h qtott15-8 (higher bits of all total transmitting reactive power) 46h (r ) qtott7-0 (lower bits of all total transmitting reactive power) 0000h - - - - - - - - 47h (r ) qtott23-16 (highest bits of all total transmitting reactive power) 0000h these registers store all total receiving reacti ve power value (q1+q2+q3+rql) and all total transmitting reactive power value (q1+q2+q3+ tql). the value is expressed in 24 bit format pulse count value of energy(add. 48h, 49h ) data bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 address a6-0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 initial value pd - ppulse13 - 8 48h ( r ) ppulse7-0 0000h qd - qpulse13-8 49h ( r ) qpulse7-0 0000h these registers store active energy pulse values and reactive energy pulse values for one second period. both active energy pulse va lues (ppulse13-ppulse0) and reactive energy pulse values (qpulse13-qpulse0) are expressed in 14 bit format. if the pulse count value is overflowed, the count value is stopped wit h a maximum value. pd(add.?48h? :bit15) shows whether the active energy pulse is receiving pulse ( pd=?0?) or transmitting pulse(pd=?1?) as same as qd(add.?49h?:bit15) shows whether th e reactive energy pulse is receiving pulse (qd=?0?) or transmitting pulse(qd=?1?). ?1? second timer is assumed that the frequency of using crystal is 12.9024mhz. if the frequency of using crystal is not 12.9024mhz but ,for example 12.8mhz, the number of pulse count will be ?1008?, which is equal to 12.9024mhz / 12.8mhz at the rated voltage an d the rated current.
[AK5602A] ms1285-e-00 2011/02 - 47 - apparent power value (add. 4a h, 4bh, 4ch, 4dh, 4eh) data bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 address a6-0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 initial value s1_15-8 (higher bits of ch1 apparent power) 4ah ( r ) s1_7-0 (lower bits of ch1 apparent power) 0000h s2_15-8 (higher bits of ch2 apparent power) 4bh ( r ) s2_7-0 (lower bits of ch2 apparent power) 0000h s3_15-8 (higher bits of ch3 apparent power) 4ch ( r ) s3_7-0 (lower bits of ch3 apparent power) 0000h ssum15-8 (higher bits of total apparent power) 4dh ( r ) ssum7-0 (lower bits of total apparent power) 0000h - - - - - - - - 4eh ( r ) - - - - - - ssum17-16 (highest bits of total apparent power) 0000h these registers store an apparent value (s1, s2, s3) on each phase and a total apparent power value. the value of apparent value on each phas e is expressed in 16 bit format and the value of total apparent value is ex pressed in 18 bit format. accumulated power pulse value (add. 50h, 51h, 52h, 53h) data bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 address a6-0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 initial value rxpo15-8 (upper bits of rpo accumulated power pulse) 50h ( r ) rxpo7-0 (lower bits of rpo accumulated power pulse) 0000h txpo15-8 (upper bits of tpo accumulated power pulse) 51h ( r ) txpo7-0 (lower bits of tpo accumulated power pulse) 0000h rxqo15-8 (upper bits of rqo accumulated power pulse) 52h ( r ) rxqo7-0 (lower bits of rqo accumulated power pulse) 0000h txqo15-8(upper bits of tqo accumulated power pulse) 53h ( r ) txqo7-0 (lower bits of tqo accumulated power pulse) 0000h these registers store upper 16 bits of accumulate d power pulse. each register is expressed in 16 bit format.
[AK5602A] ms1285-e-00 2011/02 - 48 - power factor (54h, 55h, 56h) data bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 address a6-0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 initial value - pf1_14-8(ch1 power factor) 54h ( r ) pf1_7-0(ch1 power factor) 0000h - pf2_14-8(ch2 power factor) 55h ( r ) pf2_7-0(ch2 power factor) 0000h - pf3_14-8(ch3 power factor) 56h ( r ) pf3_7-0(ch3 power factor) 0000h these registers store power factors of ch1, ch2, ch3.power factor is expressed by the value between -1 and +1. there are two differ ent ways of calculating power factor. the one is to use the apparent power, which is derived from active power and reactive power calculation. this selection of the calculation is the default setting. the other is to use the apparent power, which is derived from rm s voltage and rms current calculation. the selection is made by the pfsel (bit 6) bit of function setting register,add.?20h?. power factor is expressed in two?s complementary expression. the polarity of the reactive power in each input express whether the being derived from power factor in each input is positve or nagative. if bit3 of add. ?39h? or ?3bh? or ?3dh? is ?0?, the in the input represents positive. if not, the represents negative. power factor (-1.0 1.0) value power factor [degree] 2000h 1.0 0.0 1fffh 0.999878(8191/8192) 0.8952 1000h 0.5 60.0 0001h 0.00012207 89.993 0000h 0.0 90.0 7fffh -0.00012207 90.00699 7000h -0.5 120.0 6001h -0.999878 179.1047 6000h -1.0 180.0
[AK5602A] ms1285-e-00 2011/02 - 49 - temperature data (57h, 58h, 59h) data bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 address a6-0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 initial value - - - - - - - - 57h (r) temp7-0 (temperature data) 0080h - - - temp_coef12-8 (temperature gain coefficient) 58h (r/w) temp_coef7-0 (temperature gain coefficient) 1c2ah - - - - - - - - 59h (r/w) - - - toffset4-0 (temperature offset coefficient) 0000h temperature related data are stored in these registers. it is possible to set temp bit (bit2) with ?1? of function setting segister, add. ?20h? to measure the temperature of the lsi and the me asured temperature data is written into temperature register, add. ?57h?. temperature data can be adjust ed with the value of temperature gain coefficient register, add.?58h? and temperature offset coefficient register,add.?59h?. when modifying the values of the temperature gain coefficient register and temperature offset coefficient register, it is needed to measure vrefi voltage at room temperature first and modify the value of the temperature gain coefficient register,add.? 58h? according to the following formula. relationship between vrefi voltage and setting value of the register is expressed as follows. temp_coef = 1c2ah (vrefi voltage / 1.17v) after modifying the value of tem_coef, it is needed to measure the temperature by setting temp bit (bit2) with ?1? of function se tting register,add.?20h? to set the temperature offset coefficient. it is needed to adjust the difference after comparing this value with the value of present room temperature according to the table of temperature offset coefficient register,add.59h? below. it is needed to measure the temperature again by setting temp bit (bit2) with ?1? of function setting register,add.?20h? to confirm that an appropriate adjustment is done. as the initial value of temperature register is an invalid value, which is ?80h?, please do not use it as the temperature data. temperature register (-40 c to 85 c) : add. 57h value temperature (celsius) 7fh - - 55h 85 c - 01h 1 c 00h 0 c ffh -1 c - d8h -40 c - 80h -
[AK5602A] ms1285-e-00 2011/02 - 50 - temperature offset coefficient register (add. 59h) value adjustment temperature (degree) 0fh +15 c 01h +1 c 00h 0 c 1fh -1 c 10h -16 c measured temperature data is written into th e temperature data register,add.?57h? after the temperature adjustment above is done against the value of temperature sensor. 5.3 pga (programmable gain controller) gain can be set from ?1? to ?4? at voltage inpu t side and ?1? to ?32? at current input side. maximum input range is specified according to analogue input full-scale voltage. this makes it possible to use adc with the maximum resolution. 5.4 adc block 5.4.1 adc adc is started with rst = stby = ?h? ch1?s, ch2?s and ch3?s adc is timesharin gly processed every 16xclks. 3 channel?s adc is processed by using 4096xclks. this means that adcs for 3 channels are performed at the rate of 3.15k hz when xclk is 12.9024mhz. it usually requires about 300ms to stabilize the vref, xclk and hpf after adc is started with rst = stby = ?h?. and it is not guaranteed the accuracy of adc during this 300ms period. rst stby a /d rdy 4096xclk ch1/ch2/ch3 3820xclk fig.8 adc timing ch1/ch2/ch3 ch1/ch2/ch3 ch1/ch2/ch3
[AK5602A] ms1285-e-00 2011/02 - 51 - 5.4.2 calibration of adcs calibration, offset adjustment of adc will be started when cal bit( bit7) of function setting register,add.?20h? is set ?1? under the condition of rst = stby = ?h?. it requires 4096 xclks to complete the calib ration and adc will be restarted after the calibration. rdy signal becomes ?high? state as s oon as the calibration starts. the rms calculation and the active power to frequenc y conversion block are suspended during the calibration. the calibration op eration is not executed when only the power is applied to the lsi ( rst =?l?). hpf is not set in the default setting. in a case that hpf is not used in the system, it is recommended to execute the calibration command once or write the calibration data, which has been measured before into the offset register in order to get an accurate adc data. and in the case that hpf is used in the system, it is recommended to set a hpf after the calibration command being executed. it is needed to execute the calibration operat ion after the setting of pga. the setting of pga should be executed after more than 300ms has passed under the state of rst = stby = ?h? . rst cal (internal) a/d rdy 4096xclk ch1/ch2/ch3 3820xclk fig.9 calibration timing ch1/ch2/ch3 cal ch1/ch2/ch3
[AK5602A] ms1285-e-00 2011/02 - 52 - 5.4.3 rdy ( adc?s instantaneous value) control rdy signal for reading instantaneous values of adc is set and output by setting rdy1-0 (bit1-0)=?01? of the control setting register, add. ?21h?. when rdy becomes ?l?, it means that accurate values of registers storing adc?s value can be read out. the low level of rdy is output while ch1?s adc is executed after the adc block has started under the condition of rst = stby = ?h?. rdy signal becomes ?l? in 280xclks afte r ch1?s adc has started and returns ?h? in 3816xclks(about 295.7us). rdy remains ?h? while rst or stby is ?l?. 279 4095 0 xclk a/d ch 1/ch 2/ch 3 adc value register v1, i1, v2, i2, v3, i3 write inst. value rdy fig10 adc inst. value readout timing 280 4095 0 279 280 3816xclk v1,i1,v2,i 2,v3,i3 rewrit e inst . value ch 1/ch 2/ch 3 when the reading out data timing of instanta neous values of adcs collide with the timing of writing into instantaneous values by the lsi, invalid status (bit15) of the controlling register, add.?21h? is set. when the collision occurs, it is necessary to read the register again.
[AK5602A] ms1285-e-00 2011/02 - 53 - 5.4.4 rdy (adc?s rms value) control rdy signal for reading rms values of adc is set and output by setting rdy1-0(bit1-0)=?00? of control setting register, add. ?21h?. when rdy becomes ?l?, it means that accurate values of registers storing adc?s value can be read out. the low level of rdy is output while ch1?s adc is executed after the adc block has started under the condition of rst = stby = ?h?. rdy signal becomes ?l? in 1872xclk after ch1?s adc has started and returns ?h? in 3384xclk(about 262.3us) . rdy remains ?h? while rst or stby is ?l?. 1019 4095 0 xclk a/d ch 1/ch 2/ch 3 adc value register v1,i1,v2,i2,v3,i3 write rms value rdy fig .11 adc rms readout timing 1020 4095 0 1019 1020 33 84x clk v1,i1,v2,i2,v3,i3 rewrite rms value ch 1/ch 2/ch 3 1871 1872 when the reading out data timing of rms va lues of adcs collide with the timing of writing rms values into registers by the ls i , invalid status (bit15) of control setting register, add. ?21h? is set. when the collision occurs, it is necessary to read the register again.
[AK5602A] ms1285-e-00 2011/02 - 54 - 5.4.5 rdy (other registers: add.22h - 57h) control rdy signal for reading registers addressing ?22h ? to ?57h? is set and output by setting rdy1-0 (bit1-0)=?10? or ?11? of co ntrol setting register, add. ?21h?. when rdy becomes ?l?, it means that accurate values of various registers can be read out. the low level of rdy is output while ch1?s adc is executed after the adc block has started under the condition of rst = stby = ?h?. rdy signal becomes ?l? in 3164xclk after ch1?s adc has started and returns ?h? in 932xclk(about 72.2us). rdy remains ?h? while rst or stby is ?l?. when the reading out data timing of a register collide with the timing of writing data into the register by the lsi, invalid status (bit15) of control setting register, add.?21h? is set. when the collision occurs, it is necessary to read the register again. 31 63 4095 0 xclk adc ch 1/ch 2/ch 3 adc registers write data into registers (add. 22h to57h) by the lsi rdy fig.12 data registers readout timing 3164 4095 0 932xclk ch 1/ch 2/ch 3
[AK5602A] ms1285-e-00 2011/02 - 55 - 5.5 hpf it is possible to insert a hpf into voltage si des and current sides in order to remove dc components on input channels. this hpf is placed on a path after each adc block. this means that dc components super imposed on as one part of an input signal and produced by an adc block can be removed. hpfs are inserted into all channels of voltages and currents simultaneously. it is possible to use hpf by setting bit3=?1? of fu nction setting register, add.?20h?. hpfs are not set in the default setting with rst = ?l?. in case of using hpfs, it is recommended to set hpfs after executing the calibration command. gain and phase characteristics of the h pfs are shown from fig.13 to fig15. gain response -5 -4.5 -4 -3.5 -3 -2.5 -2 -1.5 -1 -0.5 0 0.1 1 10 100 1000 frequency [hz] magnitude [db] fig.13 gain ? frequency characteristics
[AK5602A] ms1285-e-00 2011/02 - 56 - phase response 0 1 2 3 4 5 6 7 8 9 10 0.1 1 10 100 1000 frequency [hz] phase [degrees] fig.14 phase ?frequency characteristics phase response 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 40 45 50 55 60 65 70 frequency [hz] phase [degrees] fig.15 phase ? frequency char acteristics (40hz to 70hz)
[AK5602A] ms1285-e-00 2011/02 - 57 - 5.6 rms calculation rms calculation block calculates rms value of v1, i1, v2, i2, v3 and i3 from adc value. these values can be read from rms registers. rms calculation flow is shown in fig.16 (1) to calculate square value of v1 (i1, v2, i2, v3, i3) (2) averaging (3) to calculate the square root fig.16 rms calculation flow lpf rms v1 (i1, v2, i2, v3, i3) (1) (2) (3)
[AK5602A] ms1285-e-00 2011/02 - 58 - 5.7 active power and reactive power to frequency converter xp+rpl or -xp+tpl data, which consists of significant 24bit, is supplied to active or reactive frequency converter at the rate of 3.15khz. (note 1) active or reactive power to frequency converter is making an arithmetic operation at the rate of 16/3 (16.8khz) and produces rpo (rqo), tpo (tqo), rpst (rqst) and tpst (tqst) output. active or reactive power to frequency converter stops its operation with rst = ?l? or stby = ?l? or dis = ?l?. (note 1) the structure of xp+rpl 22 bit 8 bit 0 21 0 7 xp rpl +) 24 bit 0 23 xp+rpl it is possible to select an apparent power as an input of reactive power to frequency converter by setting ?1? of bi t14 at power addition ?disable? setting register, add.?1dh?. furthermore, as an apparent power does not have the light load register, 22 bit apparent power value is shift in two bits left. as the result, 24 bit format data is input at alu and is converted into th e power pulse. xp+rpl 24 bi t reg if a w rp th en po ? 1 else po ? 0 if po fre que ncy t rp then rpo ? 0 rpst ? 0 else rpo ? po rpst ? 1 rp: rated value w rp rp : starting value t rp rpo rpst 3.15khz 16.8khz alu (28 bit) magnitude comparator creep protection -xp+tpl 24 bi t reg if b w tp th en po ? 1 else po ? 0 if po fre que ncy t tp then tpo ? 0 tpst ? 0 else tpo ? po tpst ? 1 tp : ra ted va lue w tp tp: starting value t tp tpo tpst fig.17 active power to frequency conversion if po = 1 th en a ? a+xp+rpl?w rp else a ? a+xp+rpl po a if po = 1 th en b ? b?xp+tpl?w tp else b ? b?xp+tpl po b
[AK5602A] ms1285-e-00 2011/02 - 59 - 7ffffffh 0000000h f000000h w rp (w tp ) underflow rpo (tpo, rqo, tqo) 59.5u s rpst (tpst, rqst, tqst) t rp (t tp ,t rq ,t tq ) when alu?s underflow occurs, the 28 bit register is reset. fig.18 rpo (tpo, rqo, tqo) output timing
[AK5602A] ms1285-e-00 2011/02 - 60 - 5.8 frequency pulse output of v1, v2 and v3 the frequencies of voltage inputs are detected, being based on adc value of v1, v2 and v3. for example, when the rising threshold value of f1, f2,and f3 is set at ?3000h? and the falling threshold value is set at ?2000h?, the waveform will be shown below. when v1, v2, v3 equals or greater than ?3000h?, fn (n=1, 2, 3) becomes ?h?. when v1, v2, v3 equals or smaller than ?2000h?, fn (n=1, 2, 3) becomes ?l?. this function is stopped at rst = ?l? or stby = ?l?. 7fffh v1(v2,v3 ) 3000h 2000h 0000h 8000h f1(f2,f3) fig.19 v1(v2,v3) frequency pulse output
[AK5602A] ms1285-e-00 2011/02 - 61 - 5.9 the way of vari ous system calibrations 5.9.1 calibration procedures of active power and reactive power (japanese specification) japanese standard of power me tering specifies that 1000 of power pulses per one second should be output when rated input voltages and currents are applied to the system. AK5602A provides an easy calibration meth od to comply with the specification. by adjusting rated active or reactive power threshold value in receiving and transmitting side, the accuracy of the equipment would be attained. general way of the calibration is described below. (1) power on the system. (2) to control rst = ?h? (3) to control stby = ?h? (4) to control dis = ?h? (5) to write ?0080h? at function setting re gister, add. ?20h? to calibrate adcs (6) to write ?0008h? at function setting register, ad d. ?20h? to insert hp f on each voltage and current input (7) when calibrating receiving active power, apply 50hz or 60hz of 0.35vrms(0.5vop) ac signal to each current and voltage input. the phase difference between voltage and current of the signal on each channel should be ?0? degree. this means that the power factor of each channel should be ?1.0?. the amplitude of the signal should be 0.35vrms when the pga is set 1. if the value of pga is set other value rather than 1 , the amplitude of the signal should be changed accordingly. for instance, if the pga set 2, the amplitude of the signal should be the half of 0.35vrms. under the condition, the number of output pulses at rpo pin is counted over checking rpst flag and should be adjusted until the number equals to 1000 for one second by modifying the value of rp rated active power threshold value register , add.?00h? and ?01h?. (8) when calibrating tranmitting active power, apply 50hz or 60hz of 0.35vrms(0.5vop) ac signal to each current and voltage input. the phase difference between voltage and current of the signal on each channel should be set at ?180? degree. this means that the power factor of each channel should be ?-1.0?. under the condition, the number of output pulses at tpo pin is counted over checking tpst flag and should be adjusted until the number equals to 1000 for one second by modi fying the value of tp rated active power threshold value register, add. ?02h? and ?03h?. (9) when calibrating receiving reactive power, apply 50hz or 60hz of 0.35vrms(0.5vop) ac signal to each current and voltage input. the phase difference between voltage and current of the signal on each channel should be ?90? degree. this means that the power factor of each channel should be 0. the amplitude of the signal should be 0.35vrms when the pga is set 1. if the value of pga is set other value rather than 1 , the amplitude of the signal should be changed accord ingly. for instance, if the pga set 2, the amplitude of the signal should be the half of 0.35vrms. under the condition, the number of output pulses at qpo pin is counted over checking rqst flag and should be adjusted until the number equals to 1000 for one second by modify ing the value of rq rated reactive power threshold value register, add.?04h? and ?05h?. (10) when calibrating tranmitting reactive powe r, apply 50hz or 60hz of 0.35vrms(0.5vop) ac signal to each current and voltage inpu t. the phase difference between voltage and current of the signal on each channel should be ?270? degr ee. this means that the power factor of each channel should be ?0?. under the condition, the number of output pulses at
[AK5602A] ms1285-e-00 2011/02 - 62 - tqo pin is counted over checking tqst flag and should be adjusted until the number equals to 1000 for every one second by modi fying the value of tq rated active power threshold value register,add. ?06h? and ?07h?. (11) it is possible to use pulse count values,add. ?48h? and ?49h? as the mothod of measuring the number of output pulses instead of counting the number of output pulses from pulse output pins(rpo, tpo, rqo, tqo). in this case, the inside timer of the AK5602A is used for one second timer and the value of the time r will be changed according to the frequency of using crystal. AK5602A defines that one second timer is attained when 12.9024mhz crystal is used. 5.9.2 initial value of rated power thre shold value (japanese specification) the initial value of rated power threshold va lue is set so that 1000 power pulses for one second would be output when the half of full scale ac signal is applied to each current input and each voltage input. the initial value is calculated as follows. power value per channel is expressed as follows. xp 1 =1/2 vin iin ,where vin = maximum voltage input ( 1.0vpp) iin = maximum current input ( 1.0vpp) initial value of rated power threshold value is defined when half of maximum input voltage and maximum input current is applied. input voltage and current per channel is vin = 1/2 (2^15) = 16384 iin = 1/2 (2^17) = 65536 and the bit width of vin iin is 34 bit width, which is 16bit + 18bit, but it is needed to be shrinked to 20bit wide by taking upper 20 bit and the result should be devided by 2^13. so, power value per channel is xp 1 = (1/2) 16384 65536 (1/(2^13)) = 65536 in a case that the same signal is ap plied to all 3ch, total power would be xp = 65536 3=196608 the light load value is added to the xp, so the relsult is shifted left by 2 bit. in a case of calculating receiving active po wer, using light load power value is rpl. xp = xp + rpl = xp 4 = 786432 this value is accumulated at the rate of 16.8 khz and the pulse is output 1000 pulses per one second. so, the enegy, w is described below. w = (xp + rpl) 16.8 = 13212057 = c99999h this value is an initial value of receiv ing rated active powe r threshold value. this initial value is also applied to the init ial value of transmitting rated active power threshold value, receiving rated reactive po wer threshold value and transmitting rated reactive power threshold value. 5.9.3 calibration procedures of active powe r and reactive power (iec specification) in iec specification, the specification of creepin g, starting current, pulse outputs is different from that of japanese standard. to comply with the iec standa rd, it is needed to change initial values of some regist ers. the following example show s that 1000 of power pulses per one second are output and general relationship between power pulses and rated power threshold value. please calibrate the energy of the system by adjusting rated power threshold values. (1) power on the system. (2) to control rst = ?h? to set registers to comply with the iec standard.
[AK5602A] ms1285-e-00 2011/02 - 63 - 1. to set the starting power threshold value re gister ?o? second : ?ffffh? at starting power threshold value register,add. ?08h? 2. to set the accumulation frequency of iec power pulse width setting register ?4.2khz? : ?8000h? at iec power puls e width setting register,add. ?1fh? 3. to set the function setting register ?i ec creeping threshold value? : ?0010h? at function setting register,add. ?20h? (3) to set rated active or reactive power threshold values in receiving and transmitting side so that 1000 pulses per second would be output. in this case , it is assumed that using crystal frequency is 12.9024mhz. when setting the iec standard mode, the relationship between the number of pulses and rated power th reshold value is expressed as follows. f (the number of pulses) = 3225600 / w (rated power threshold value) w = 3225600 / 1000 = 3225.6 = 0c99h ?0c99h? is set at add.?00h?, ?02h?, ?04h?, ?06h? and ?0000h? is set at add. ?01h?, ?03h?, ?05h?, ?07h?. (4) to control stby = ?h? (5) to control dis = ?h? (6) to write ?0080h? at function setting register,add.?20h? to calibrate adcs (7) to write ?0008h? at function setting register,a dd.?20h? to insert hpf on each voltage and current input (8) when calibrating receiving active power, apply 50hz or 60hz of 0.35vrms (0.5vop) ac signal to each current and voltage input. the phase difference between voltage and current of the signal on each channel should be ?0? degree. this means that the power factor of each channel should be ?1.0?. the amplitude of the signal should be 0.35vrms when the pga is set 1. if the value of pga is set other value rather than 1, the amplitude of the signal should be changed a ccordingly. for instance, if the pga is set 2, the amplitude of the signal should be the half of 0.35vrms. under the condition, the number of output pulses at rpo pin is counted and should be adjusted until the number equals to 1000 for every one second by modi fying the value of rp rated active power threshold value register at add.?00h? and ?01h?. (9) when calibrating tranmitting active power, apply 50hz or 60hz of 0.35vrms (0.5vop) ac signal to each current and voltage input. the phase difference between voltage and current of the signal on each channel should be ?180? degr ee. this means that the power factor of each channel should be ?-1.0?. under the condition, the number of output pulses at tpo pin is counted and should be adjusted until the number equals to 1000 for every one second by modifying the value of tp rated active power threshold value register at add. ?02h? and ?03h?. (10) when calibrating receiving reactive power, apply 50hz or 60hz of 0.35vrms (0.5vop) ac signal to each current and voltage inpu t. the phase difference between voltage and current of the signal on each channel should be ?90? degree. this means that the power factor of each channel should be 0. the amplitude of the signal should be 0.35vrms when the pga is set 1. if the value of pga is set other value rather than 1 , the amplitude of the signal should be changed accord ingly. for instance, if the pga set 2, the amplitude of the signal should be the half of 0.35vrms. under the condition, the number of output pulses at qpo pin is counted and should be adjusted until the number is equal to 1000 for one second by modifying the value of rq rate d reactive power threshold value register at add.?04h? and ?05h?.
[AK5602A] ms1285-e-00 2011/02 - 64 - (11) when calibrating tranmitting active power, apply 50hz or 60hz of 0.35vrms(0.5vop) ac signal to each current and voltage inpu t. the phase difference between voltage and current of the signal on each channel should be ?270? degr ee. this means that the power factor of each channel should be ?0?. under the condition, the number of output pulses at tqo pin is counted and should be adjusted until the number is equal to 1000 for one second by modifying the value of tq rated active power threshold value register at add. ?06h? and ?07h?. (12) it is possible to use pulse count values at add.?48h? and ?49h? as the mothod of measuring the number of output pulses instea d of counting the number of output pulses from pulse output pins (rpo, tpo, rqo, tqo). in this case, the inside timer in the AK5602A is used for one second timer and the value of the ti mer will be changed according to the frequency of using crystal. AK5602A define s that one second timer is attained when 12.9024mhz crystal is used. (13) in iec setting mode, the pulse frequency per second, f is expressed as follows. f (the number of pulses) = 3225600 / w (rated power threshold value) pulse frequency,f is varied according to the value of rated power threshold in the following. 0.048065186263hz f 8400hz -------------------------------(a) 5.9.4 initial value of rated power threshold value (i ec specification) the initial value of rated power threshold value is set in japanese specification so that 1000 power pulses for one second would be output wh en a half of full-scale of 50 to 60 hz of ac signal is applied to each current input and ea ch voltage input. when AK5602A is used in iec mode, related registers and rated power threshol d value should be modified. the initial value in iec standard is calculated as follows. power value per channel is xp 1 =1/2 vin iin ,where vin = maximum voltage input ( 1.0vpp) iin = maximum current input ( 1.0vpp) initial value of rated power threshold value is defined when half of maximum input voltage and maximum input current is applied. input voltage and current per channel is vin = 1/2 (2^15) = 16384 iin = 1/2 (2^17) = 65536 and the bit width of vin iin is 34 bit wide, which is 16bit + 18bit but it is needed to be shrinked to 20bit wide by taking upper 20 bit and the result should be devided by 2^13. so, power value per channel is xp 1 = (1/2) 16384 65536 (1/(2^13)) = 65536 in a case that the same signal is applied to all 3ch, total power is expressed as follows. xp = 65536 3=196608 the light load value is added to the xp, so the relsult is shifted left by 2 bit. in a case of calculating receiving active po wer, using light load power value is rpl. xp = xp + rpl = xp 4 = 786432 and in iec mode, pulse frequency,f is f = 4200 p / (w 1024) ,where p = total power, w = rated power threshold value when half of maximum input voltage and maximum input current is applied to each channel , f = 4200 786432 / w 1024 = 3225600 / w -------------------------------------(b) in other expression, w = 3225600 / f maximum value of w(rated power threshold) is 3fffffh (67108863) and pulse frequency at the value, f min is expressed as follows.
[AK5602A] ms1285-e-00 2011/02 - 65 - f min = 3225600 / 67108863 = 0.048065186hz when the pulse frequency,f is 1000, w = 3225600 / 1000 = 3225.6 = c99h in iec mode, the value of pulse frequency should be set from around 0.1hz to 2 or 3hz. the value of rated power threshold can be set according to the equation (a) and (b). explained setting rated power thereshold method is applied to transmitting active power threshold value, receiving reactive power thre shold value and transmi tting reactive power threshold value as well. 5.9.5 calibration measure between input voltage and input current on each channel (1) please apply the rated input voltage and rated input current on each channel of the system. in order to calibrate the phase error at only the 1 st channel, the incoming signal at 2 nd channel and 3 rd channel should be shortened by using shorting bits ?zv2?, ?zv3?, ?zi2?, ?zi3? at function setting register ?20h? lest should powers other than 1 st channel be accumulated. (2) the number of receiving power pulses when voltage input and current input at power factor being ?1? is defined as ?a?. the number of receiving power pulses when voltage input and current input at power factor being ?0 .5? is defined as ?b?. the phase error, is expresed as follows. = ( b - a /2 ) / (a/2) therefore the phase difference, (degree) is = -sin -1 ( / 3) to set value at power factor ad justment value setting register (add. 0dh, 0eh, 0fh) so that is equal to zero. when input signal freq uency is 50hz and using crystal frequency is 12.9024 mhz in AK5602A, the phase adjustment range, is expressed as followed. -613.84us ( -11.05 ) +613.84us (+11.05 ) it is possible to adjust the phase er ror with the resolution of 1.25us (0.0225 ) per step. (3) the phase error of 2 nd channel and 3 rd channel is also adjusted in the same manner as the 1 st channel. adjustment range and resolution are affected by usin g crystal frequency. for example, the resolution of calibration range at 12.8mhz crystal is 1.25us (0.0225 ). 5.9.6 full scale vaue adjustment this function is to adjust the variations prod uced by pga and / or vref from ideal value so that the result of adc has an ideal adc code wh en a half of full-scale dc voltage, 0.5 v is applied to each voltage and current channel. when using this function, the gain of all voltage channels should be the same value as well as the gain of all current channels. the gain between current and voltage can be changed. it is noted that after the adjustment, every calculation including an instantaneous value, rms value and active & reactive power is affected. this is the only way to adjust rms voltage value and rms current value. the adjustment of gain on voltage side is perfor med by setting ?1? to ?bit0?, fullv of function setting register at address ?20h?. and the adjustment of gain on current side is performed by setting ?1? to ?bit1?, fulli of function setting regist er at address ?20h?. after the execution of this command, the adjustme nt values can be read from add.?16h?, ?17h?, ?18h?. it is also possible to set the values as well by writing the values directly into these registers.
[AK5602A] ms1285-e-00 2011/02 - 66 - input circuits v1p v2p v3p vin i1p i1n i2p i2n i3p i3n n 1 2 3 n 1 2 3 xout avdd vs vrefi vrefo vcom dvdd i1p vin xin dvss avss 12.8mhz 15pf 15pf 1m 0.1uf 0.1uf 0.1uf 4.7uf + 0.1uf 4.7 example of voltage inputs(registors) example of current inputs (cts) (2) it can not be guranteed that the value of resistors and capacitors around the crystal oscillator is the best constants. it is recommended to confirm the technical data of manufactures of crystal oscillators. power line (3phase 4line) 10uf + 10uf + 0.1uf 2.7v to 5.25v 6. recommended circuit diagram around AK5602A 33nf 33nf same as v3 same as v3 500 500 33nf 33nf 500 500 same as i3n same as i3n same as i3p same as i3p (1) input circuits to power lines above are only examples. it is recommended that capacitors and resistors should be selected so that the frequency of anti-aliasing filters is higher to prevent from producing the phase error.
[AK5602A] ms1285-e-00 2011/02 - 67 - 7.0 package conditions 1) shape: lqfp 2) pin count: 48pin 3) marking: marking of the package is specified as follows. a. no1 pin indication: there is a round mark and cutting edge. b. akm?s logo and product name c. date code xxxxxxx ( 7 digits) xxxxxxx akm AK5602A 7.1 package outline 1 12 48 13 7.0 9.0 0. 2 7.0 9.0 0. 2 0.2 2 0.08 48pin lqfp (unit: mm) 0.10 37 12 24 25 36 0.09 0.2 2 1.4 0.10 0.07 1.70ma x 0 10 0.10 m 0.3 0.75 0.5
[AK5602A] ms1285-e-00 2011/02 - 68 - revision history date revision reason page contents 01/02/03 00 first edition important notice z these products and their specifications ar e subject to change without notice. when you consider any use or application of these pr oducts, please make inquiries the sales office of asahi kasei microdevices corporation (akm) or authorized distributors as to current status of the products. z descriptions of external circuits, application circuits, software and other related information contained in this document are provided only to illustrate the operation an d application examples of the semiconductor products. you are fully responsible for the inco rporation of these external circuits , application circuits, software and other related information in the design of your equipments. akm assumes no responsibility for any losses incurred by you or third parties arising from the use of these information herein. akm assumes no liability for infringement of any patent, intellectual property, or other rights in the application or use of such information contained herein. z any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. z akm products are neither intended nor authorized for use as critical components note1) in any safety, life support, or other hazard related device or system note2) , and akm assumes no responsibility for such use, except for the use approved with the express written co nsent by representative dir ector of akm. as used here: note1) a critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectivene ss of the device or system containing it, and which must therefore meet ve ry high standards of performance and reliability. note2) a hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medi cine, aerospace, nuclear en ergy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. z it is the responsibility of the buyer or distributor of akm products, who distributes, disposes of, or otherwise places the product with a thir d party, to notify such third party in ad vance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold akm harmless from any and all claims arising from the use of said product in the absence of such notification.

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